drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++++++--- drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 2 ++ 2 files changed, 11 insertions(+), 3 deletions(-)
The A750 uses a different counter register as used on the downstream
driver:
static u64 gen7_9_0_read_alwayson(struct adreno_device *adreno_dev)
{
...
/* Always use the GMU AO counter when doing a AHB read */
gmu_core_regread(device, GEN7_GMU_CX_AO_COUNTER_HI, &hi);
gmu_core_regread(device, GEN7_GMU_CX_AO_COUNTER_LO, &lo);
...
}
gen7_reg.h:#define GEN7_GMU_CX_AO_COUNTER_LO 0x1f880
gen7_reg.h:#define GEN7_GMU_CX_AO_COUNTER_HI 0x1f881
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Changes in v2:
- Fix swapped H/L registers in XML
- Link to v1: https://patch.msgid.link/20260908-topic-sm8650-gmu-a750-timestamp-reg-v1-0-284880d6e68b@linaro.org
---
Neil Armstrong (2):
drm/msm/a6xx: Add CX AO Counter registers used for a750 GPUs
drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++++++---
drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 2 ++
2 files changed, 11 insertions(+), 3 deletions(-)
---
base-commit: df2908090cda368b01ff43709f51890076c56157
change-id: 20260908-topic-sm8650-gmu-a750-timestamp-reg-2e7575e6279d
Best regards,
--
Neil Armstrong <neil.armstrong@linaro.org>
On 9/9/2026 6:37 PM, Neil Armstrong wrote:
> The A750 uses a different counter register as used on the downstream
> driver:
>
> static u64 gen7_9_0_read_alwayson(struct adreno_device *adreno_dev)
> {
> ...
> /* Always use the GMU AO counter when doing a AHB read */
> gmu_core_regread(device, GEN7_GMU_CX_AO_COUNTER_HI, &hi);
> gmu_core_regread(device, GEN7_GMU_CX_AO_COUNTER_LO, &lo);
> ...
> }
>
> gen7_reg.h:#define GEN7_GMU_CX_AO_COUNTER_LO 0x1f880
> gen7_reg.h:#define GEN7_GMU_CX_AO_COUNTER_HI 0x1f881
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
This is correct. There was a register shuffling in the gmu_cx block in a750 and another shuffling later in gen8 family.
It is a good idea to review other GMU_CX* register offsets with KGSL. Also, please consider including a fixes tag.
-Akhil.
> ---
> Changes in v2:
> - Fix swapped H/L registers in XML
> - Link to v1: https://patch.msgid.link/20260908-topic-sm8650-gmu-a750-timestamp-reg-v1-0-284880d6e68b@linaro.org
>
> ---
> Neil Armstrong (2):
> drm/msm/a6xx: Add CX AO Counter registers used for a750 GPUs
> drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs
>
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++++++---
> drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 2 ++
> 2 files changed, 11 insertions(+), 3 deletions(-)
> ---
> base-commit: df2908090cda368b01ff43709f51890076c56157
> change-id: 20260908-topic-sm8650-gmu-a750-timestamp-reg-2e7575e6279d
>
> Best regards,
> --
> Neil Armstrong <neil.armstrong@linaro.org>
On 9/15/26 23:20, Akhil P Oommen wrote:
>
>
> On 9/9/2026 6:37 PM, Neil Armstrong wrote:
>> The A750 uses a different counter register as used on the downstream
>> driver:
>>
>> static u64 gen7_9_0_read_alwayson(struct adreno_device *adreno_dev)
>> {
>> ...
>> /* Always use the GMU AO counter when doing a AHB read */
>> gmu_core_regread(device, GEN7_GMU_CX_AO_COUNTER_HI, &hi);
>> gmu_core_regread(device, GEN7_GMU_CX_AO_COUNTER_LO, &lo);
>> ...
>> }
>>
>> gen7_reg.h:#define GEN7_GMU_CX_AO_COUNTER_LO 0x1f880
>> gen7_reg.h:#define GEN7_GMU_CX_AO_COUNTER_HI 0x1f881
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>
> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
>
> This is correct. There was a register shuffling in the gmu_cx block in a750 and another shuffling later in gen8 family.
>
> It is a good idea to review other GMU_CX* register offsets with KGSL. Also, please consider including a fixes tag.
OK thanks,
Neil
>
> -Akhil.
>
>
>> ---
>> Changes in v2:
>> - Fix swapped H/L registers in XML
>> - Link to v1: https://patch.msgid.link/20260908-topic-sm8650-gmu-a750-timestamp-reg-v1-0-284880d6e68b@linaro.org
>>
>> ---
>> Neil Armstrong (2):
>> drm/msm/a6xx: Add CX AO Counter registers used for a750 GPUs
>> drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs
>>
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++++++---
>> drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 2 ++
>> 2 files changed, 11 insertions(+), 3 deletions(-)
>> ---
>> base-commit: df2908090cda368b01ff43709f51890076c56157
>> change-id: 20260908-topic-sm8650-gmu-a750-timestamp-reg-2e7575e6279d
>>
>> Best regards,
>> --
>> Neil Armstrong <neil.armstrong@linaro.org>
>
Hi Rob, Akhil,
On 9/9/26 15:07, Neil Armstrong wrote:
> The A750 uses a different counter register as used on the downstream
> driver:
>
> static u64 gen7_9_0_read_alwayson(struct adreno_device *adreno_dev)
> {
> ...
> /* Always use the GMU AO counter when doing a AHB read */
> gmu_core_regread(device, GEN7_GMU_CX_AO_COUNTER_HI, &hi);
> gmu_core_regread(device, GEN7_GMU_CX_AO_COUNTER_LO, &lo);
> ...
> }
>
> gen7_reg.h:#define GEN7_GMU_CX_AO_COUNTER_LO 0x1f880
> gen7_reg.h:#define GEN7_GMU_CX_AO_COUNTER_HI 0x1f881
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> Changes in v2:
> - Fix swapped H/L registers in XML
> - Link to v1: https://patch.msgid.link/20260908-topic-sm8650-gmu-a750-timestamp-reg-v1-0-284880d6e68b@linaro.org
Gentle ping for review
Thanks,
Neil
>
> ---
> Neil Armstrong (2):
> drm/msm/a6xx: Add CX AO Counter registers used for a750 GPUs
> drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs
>
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++++++---
> drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 2 ++
> 2 files changed, 11 insertions(+), 3 deletions(-)
> ---
> base-commit: df2908090cda368b01ff43709f51890076c56157
> change-id: 20260908-topic-sm8650-gmu-a750-timestamp-reg-2e7575e6279d
>
> Best regards,
> --
> Neil Armstrong <neil.armstrong@linaro.org>
>
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