This patch series adds MediaTek mt6572 efuse support. Unlike newer SoCs,
its efuse controller doesn't work properly with 8-bit reads, leading to
invalid data with current mtk-efuse driver implementation.

This behavior can be observed with devmem (0x10009174 and 0x10009178 are
thermal calibration cells):
~ # devmem 0x10009174 32
0x00CDD4CD
~ # devmem 0x10009178 32
0x0F76865D
~ # devmem 0x10009174 8
0xCD
~ # devmem 0x10009175 8
0x00
~ # devmem 0x10009176 8
0x00
~ # devmem 0x10009177 8
0x00
~ # devmem 0x10009178 8
0x5D
~ # devmem 0x10009179 8
0x00
~ # devmem 0x1000917a 8
0x00
~ # devmem 0x1000917b 8
0x00

Patch 1 adds dt-bindings compatible for the mt6572,
Patch 2 adds platform data option to use aligned 32-bit reads instead
of plain readb().
Patch 3 adds platform data for mt6572 SoC.

Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
Changes in v3:
- Pick up Rob's r-b tag for dt-bindings
- Patch 2 and 3 unchanged, for some reason cover letter and patch 1 were
missing on the web mirror...
- Link to v2: https://patch.msgid.link/20260724-6572-nvmem-v2-0-e58d16a29621@protonmail.com

Changes in v2:
- dt-bindings: make mediatek,mt6572-efuse standalone compatible
- Driver: add 'mtk_reg_read_aligned' helper instead of modifying 'mtk_reg_read'
- Link to v1: https://patch.msgid.link/20260715-6572-nvmem-v1-0-9c13be99d077@protonmail.com

---
Roman Vivchar (3):
      dt-bindings: nvmem: mediatek: efuse: add mt6572
      nvmem: mtk-efuse: add support for 32-bit aligned reads
      nvmem: mtk-efuse: add mt6572 support

 .../devicetree/bindings/nvmem/mediatek,efuse.yaml  |  5 ++-
 drivers/nvmem/mtk-efuse.c                          | 41 +++++++++++++++++++++-
 2 files changed, 44 insertions(+), 2 deletions(-)
---
base-commit: 8cd9520d35a6c38db6567e97dd93b1f11f185dc6
change-id: 20260710-6572-nvmem-eb98c7a73351

Best regards,
--  
Roman Vivchar <rva333@protonmail.com>

On 9/9/26 11:48 AM, Roman Vivchar via B4 Relay wrote:
> This patch series adds MediaTek mt6572 efuse support. Unlike newer SoCs,
> its efuse controller doesn't work properly with 8-bit reads, leading to
> invalid data with current mtk-efuse driver implementation.
> 
> This behavior can be observed with devmem (0x10009174 and 0x10009178 are
> thermal calibration cells):
> ~ # devmem 0x10009174 32
> 0x00CDD4CD
> ~ # devmem 0x10009178 32
> 0x0F76865D
> ~ # devmem 0x10009174 8
> 0xCD
> ~ # devmem 0x10009175 8
> 0x00
> ~ # devmem 0x10009176 8
> 0x00
> ~ # devmem 0x10009177 8
> 0x00
> ~ # devmem 0x10009178 8
> 0x5D
> ~ # devmem 0x10009179 8
> 0x00
> ~ # devmem 0x1000917a 8
> 0x00
> ~ # devmem 0x1000917b 8
> 0x00
> 
> Patch 1 adds dt-bindings compatible for the mt6572,
> Patch 2 adds platform data option to use aligned 32-bit reads instead
> of plain readb().
> Patch 3 adds platform data for mt6572 SoC.
> 
> Signed-off-by: Roman Vivchar <rva333@protonmail.com>
> ---
> Changes in v3:
> - Pick up Rob's r-b tag for dt-bindings
> - Patch 2 and 3 unchanged, for some reason cover letter and patch 1 were
> missing on the web mirror...
> - Link to v2: https://patch.msgid.link/20260724-6572-nvmem-v2-0-e58d16a29621@protonmail.com
> 
> Changes in v2:
> - dt-bindings: make mediatek,mt6572-efuse standalone compatible
> - Driver: add 'mtk_reg_read_aligned' helper instead of modifying 'mtk_reg_read'
> - Link to v1: https://patch.msgid.link/20260715-6572-nvmem-v1-0-9c13be99d077@protonmail.com
> 
> ---
> Roman Vivchar (3):
>       dt-bindings: nvmem: mediatek: efuse: add mt6572
>       nvmem: mtk-efuse: add support for 32-bit aligned reads
>       nvmem: mtk-efuse: add mt6572 support
> 

Doesn't apply cleanly pl resend.

--srini
>  .../devicetree/bindings/nvmem/mediatek,efuse.yaml  |  5 ++-
>  drivers/nvmem/mtk-efuse.c                          | 41 +++++++++++++++++++++-
>  2 files changed, 44 insertions(+), 2 deletions(-)
> ---
> base-commit: 8cd9520d35a6c38db6567e97dd93b1f11f185dc6
> change-id: 20260710-6572-nvmem-eb98c7a73351
> 
> Best regards,
> --  
> Roman Vivchar <rva333@protonmail.com>
> 
>

On 9/9/26 12:48, Roman Vivchar via B4 Relay wrote:
> This patch series adds MediaTek mt6572 efuse support. Unlike newer SoCs,
> its efuse controller doesn't work properly with 8-bit reads, leading to
> invalid data with current mtk-efuse driver implementation.
> 

Series is

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Cheers,
Angelo


> This behavior can be observed with devmem (0x10009174 and 0x10009178 are
> thermal calibration cells):
> ~ # devmem 0x10009174 32
> 0x00CDD4CD
> ~ # devmem 0x10009178 32
> 0x0F76865D
> ~ # devmem 0x10009174 8
> 0xCD
> ~ # devmem 0x10009175 8
> 0x00
> ~ # devmem 0x10009176 8
> 0x00
> ~ # devmem 0x10009177 8
> 0x00
> ~ # devmem 0x10009178 8
> 0x5D
> ~ # devmem 0x10009179 8
> 0x00
> ~ # devmem 0x1000917a 8
> 0x00
> ~ # devmem 0x1000917b 8
> 0x00
> 
> Patch 1 adds dt-bindings compatible for the mt6572,
> Patch 2 adds platform data option to use aligned 32-bit reads instead
> of plain readb().
> Patch 3 adds platform data for mt6572 SoC.
> 
> Signed-off-by: Roman Vivchar <rva333@protonmail.com>
> ---
> Changes in v3:
> - Pick up Rob's r-b tag for dt-bindings
> - Patch 2 and 3 unchanged, for some reason cover letter and patch 1 were
> missing on the web mirror...
> - Link to v2: https://patch.msgid.link/20260724-6572-nvmem-v2-0-e58d16a29621@protonmail.com
> 
> Changes in v2:
> - dt-bindings: make mediatek,mt6572-efuse standalone compatible
> - Driver: add 'mtk_reg_read_aligned' helper instead of modifying 'mtk_reg_read'
> - Link to v1: https://patch.msgid.link/20260715-6572-nvmem-v1-0-9c13be99d077@protonmail.com
> 
> ---
> Roman Vivchar (3):
>        dt-bindings: nvmem: mediatek: efuse: add mt6572
>        nvmem: mtk-efuse: add support for 32-bit aligned reads
>        nvmem: mtk-efuse: add mt6572 support
> 
>   .../devicetree/bindings/nvmem/mediatek,efuse.yaml  |  5 ++-
>   drivers/nvmem/mtk-efuse.c                          | 41 +++++++++++++++++++++-
>   2 files changed, 44 insertions(+), 2 deletions(-)
> ---
> base-commit: 8cd9520d35a6c38db6567e97dd93b1f11f185dc6
> change-id: 20260710-6572-nvmem-eb98c7a73351
> 
> Best regards,
> --
> Roman Vivchar <rva333@protonmail.com>