The MDM9607 APCS IPC register is at offset 0x8 in the KPSS global block.
Its CPU clock controller is in a separate block, so the existing MSM8994
APCS match data can be used without registering a clock device.

Document the MDM9607 compatible with the MSM8994 fallback so the existing
driver match data can be reused.

Signed-off-by: Dmitry Sinyavin <sinyavin@gmail.com>
---
Validated with dt_binding_check, including yamllint, and positive and
negative DTB tests for the compatible string combination. Existing
MSM8974, MSM8976 and MSM8994 APCS nodes also pass schema validation.

Built the APCS IPC driver for ARM (multi_v7_defconfig) and arm64 (defconfig)
with Clang and W=1.

 .../devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
index 39bc374300c3..e87373054d76 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -33,6 +33,7 @@ properties:
           - const: syscon
       - items:
           - enum:
+              - qcom,mdm9607-apcs-kpss-global
               - qcom,msm8974-apcs-kpss-global
               - qcom,msm8976-apcs-kpss-global
           - const: qcom,msm8994-apcs-kpss-global

base-commit: 14af7a96afa39f4f3c1972705489b9ba15c01857

On 9/8/26 10:11 AM, Dmitry Sinyavin wrote:
> The MDM9607 APCS IPC register is at offset 0x8 in the KPSS global block.
> Its CPU clock controller is in a separate block, so the existing MSM8994
> APCS match data can be used without registering a clock device.

Aren't you going to bind one to APCS though? IIRC the setup on MDM9607
is somewhat similar to the one on 8916, although naturally a bit simpler.

+Stephan may know more

Konrad

Hi Konrad,

Thanks for the review!

I based this on the downstream MDM9607 DT and clock driver (see 
https://android.googlesource.com/kernel/msm.git/+/android-7.1.0_r0.3/arch/arm/boot/dts/qcom/mdm9607.dtsi): 
the CPU mux/divider uses a separate register resource at 0x0b010008, and 
the APCS mailbox register is at 0x0b011008. But I see your point, I 
found SDX55 is using a layout very close to what you're proposing. That 
design might be superior indeed, although both would work. Let me think 
about it a bit more and come out with v2.

Best regards,
Dmitry


08.09.2026 13:02, Konrad Dybcio wrote:
> On 9/8/26 10:11 AM, Dmitry Sinyavin wrote:
>> The MDM9607 APCS IPC register is at offset 0x8 in the KPSS global block.
>> Its CPU clock controller is in a separate block, so the existing MSM8994
>> APCS match data can be used without registering a clock device.
> 
> Aren't you going to bind one to APCS though? IIRC the setup on MDM9607
> is somewhat similar to the one on 8916, although naturally a bit simpler.
> 
> +Stephan may know more
> 
> Konrad