From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

This series adds support for the Intel SoCFPGA Agilex5 SoCDK TSN Config2
board variant, which enables gmac1 as a TSN Ethernet port alongside the
standard gmac2 port.

The TSN port (gmac1) connects to its PHY through a GMII-to-RGMII converter
implemented as FPGA soft IP. This converter provides the RGMII TX/RX clock
delays, requiring the MAC interface selector to be configured for GMII while
the PHY-facing interface is configured as RGMII without delay duplication.

Add altr,socfpga-stmmac-agilex5-tsn for that integration. It is not listed
as a DT fallback of altr,socfpga-stmmac-agilex5 because that port has no such
converter. Patch 4 adds dedicated match .data ops for the required
interface setup.

v6:
  - Put altr,socfpga-stmmac-agilex5-tsn in the same compatible enum as
    altr,socfpga-stmmac-agilex5 in the net binding, per Krzysztof Kozlowski.

v5:
  - Replace of_device_is_compatible() probe check with dedicated
    socfpga_agilex5_tsn_gmac_ops via match .data, per Krzysztof Kozlowski
    and Dinh Nguyen.
  - Drop altr,socfpga-stmmac-agilex5 fallback from the TSN compatible list
    and rewrite the net binding commit message to explain the hardware
    difference, per Krzysztof Kozlowski.

v4:
  - Fix wrong email address in Acked-by tag from Krzysztof Kozlowski on patch 1.
  - Add Reviewed-by from Andrew Lunn on patch 4.

v3:
  - Add missing Acked-by from Krzysztof Kozlowski on patch 1, inadvertently
    dropped in v2.

v2:
  - Replace mac-mode DT property with compatible string-based detection per
    Andrew Lunn's feedback.
  - Use phy-mode = "rgmii-id" to correctly reflect MAC-side delay handling.
  - Rename compatible string to altr,socfpga-stmmac-agilex5-tsn for
    consistency with existing altr,socfpga-stmmac-* compatibles.
  - Fix Makefile indentation reported by Krzysztof Kozlowski.
  - Add DT binding documentation for new net compatible string (new patch).

Nazim Amirul (4):
  dt-bindings: arm: altera: Add Agilex5 SoCDK TSN Config2 board
  arm64: dts: socfpga: agilex5: Add SoCDK TSN Config2 board
  dt-bindings: net: altr,socfpga-stmmac: Add
    altr,socfpga-stmmac-agilex5-tsn compatible
  net: stmmac: dwmac-socfpga: Add support for Agilex5 TSN GMAC with FPGA
    converter

 .../devicetree/bindings/arm/altera.yaml       |   1 +
 .../bindings/net/altr,socfpga-stmmac.yaml     |   5 +-
 arch/arm64/boot/dts/intel/Makefile            |   1 +
 .../intel/socfpga_agilex5_socdk_tsn_cfg2.dts  | 130 ++++++++++++++++++
 .../ethernet/stmicro/stmmac/dwmac-socfpga.c   |  23 +-
 5 files changed, 158 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_tsn_cfg2.dts

-- 
2.43.7

On 9/8/26 02:05, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
> 
> This series adds support for the Intel SoCFPGA Agilex5 SoCDK TSN Config2
> board variant, which enables gmac1 as a TSN Ethernet port alongside the
> standard gmac2 port.
> 
> The TSN port (gmac1) connects to its PHY through a GMII-to-RGMII converter
> implemented as FPGA soft IP. This converter provides the RGMII TX/RX clock
> delays, requiring the MAC interface selector to be configured for GMII while
> the PHY-facing interface is configured as RGMII without delay duplication.
> 
> Add altr,socfpga-stmmac-agilex5-tsn for that integration. It is not listed
> as a DT fallback of altr,socfpga-stmmac-agilex5 because that port has no such
> converter. Patch 4 adds dedicated match .data ops for the required
> interface setup.
> 
> v6:
>    - Put altr,socfpga-stmmac-agilex5-tsn in the same compatible enum as
>      altr,socfpga-stmmac-agilex5 in the net binding, per Krzysztof Kozlowski.
> 
> v5:
>    - Replace of_device_is_compatible() probe check with dedicated
>      socfpga_agilex5_tsn_gmac_ops via match .data, per Krzysztof Kozlowski
>      and Dinh Nguyen.
>    - Drop altr,socfpga-stmmac-agilex5 fallback from the TSN compatible list
>      and rewrite the net binding commit message to explain the hardware
>      difference, per Krzysztof Kozlowski.
> 
> v4:
>    - Fix wrong email address in Acked-by tag from Krzysztof Kozlowski on patch 1.
>    - Add Reviewed-by from Andrew Lunn on patch 4.
> 
> v3:
>    - Add missing Acked-by from Krzysztof Kozlowski on patch 1, inadvertently
>      dropped in v2.
> 
> v2:
>    - Replace mac-mode DT property with compatible string-based detection per
>      Andrew Lunn's feedback.
>    - Use phy-mode = "rgmii-id" to correctly reflect MAC-side delay handling.
>    - Rename compatible string to altr,socfpga-stmmac-agilex5-tsn for
>      consistency with existing altr,socfpga-stmmac-* compatibles.
>    - Fix Makefile indentation reported by Krzysztof Kozlowski.
>    - Add DT binding documentation for new net compatible string (new patch).
> 
> Nazim Amirul (4):
>    dt-bindings: arm: altera: Add Agilex5 SoCDK TSN Config2 board
>    arm64: dts: socfpga: agilex5: Add SoCDK TSN Config2 board
>    dt-bindings: net: altr,socfpga-stmmac: Add
>      altr,socfpga-stmmac-agilex5-tsn compatible
>    net: stmmac: dwmac-socfpga: Add support for Agilex5 TSN GMAC with FPGA
>      converter
> 


Applied patches 1,2.

Thanks,
Dinh

On Tue,  8 Sep 2026 00:05:53 -0700
muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
> Subject: [PATCH v6 0/4] Add Agilex5 SoCDK TSN Config2 board support

This is about to drop out of patchwork, and we need acks.
Please repost just patches 3,4 as a separate series for networking
(if the series is still relevant of course).

On 22/9/2026 4:39 am, Jakub Kicinski wrote:
> On Tue,  8 Sep 2026 00:05:53 -0700
> muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
>> Subject: [PATCH v6 0/4] Add Agilex5 SoCDK TSN Config2 board support
> This is about to drop out of patchwork, and we need acks.
> Please repost just patches 3,4 as a separate series for networking
> (if the series is still relevant of course).

Hi Jakub,

Will separate the series and repost it. I think its harmless because 
this feature is for tsn config 2 only and it will do nothing until DTS 
part are merge and meanwhile it shall not break any feature.

BR,

Nazim