staging: media: tegra-video: use BIT() macro instead of bitwise shift

[PATCH] staging: media: tegra-video: use BIT() macro instead of bitwise shift

Posted by Lalit Shankar Chowdhury 2 weeks, 4 days ago

Replace the remaining instances of (1 << X) with BIT(X) to follow the
kernel coding style guidelines.

Signed-off-by: Lalit Shankar Chowdhury <lalitshankarch@gmail.com>
---
 drivers/staging/media/tegra-video/tegra20.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/media/tegra-video/tegra20.c
index eb1fc5b7e2cd..2586a137d9da 100644
--- a/drivers/staging/media/tegra-video/tegra20.c
+++ b/drivers/staging/media/tegra-video/tegra20.c
@@ -177,15 +177,15 @@ enum tegra_vi_out {
 #define       CSI_SKIP_PACKET_THRESHOLD(n)		(((n) & 0xff) << 16)
 #define TEGRA_CSI_PIXEL_STREAM_CONTROL0(n)		(0x0018 + (n) * 0x2c)
 #define       CSI_PP_PAD_FRAME_PAD0S			(0 << 28)
-#define       CSI_PP_PAD_FRAME_PAD1S			(1 << 28)
+#define       CSI_PP_PAD_FRAME_PAD1S			BIT(28)
 #define       CSI_PP_PAD_FRAME_NOPAD			(2 << 28)
 #define       CSI_PP_HEADER_EC_ENABLE			BIT(27)
 #define       CSI_PP_PAD_SHORT_LINE_PAD0S		(0 << 24)
-#define       CSI_PP_PAD_SHORT_LINE_PAD1S		(1 << 24)
+#define       CSI_PP_PAD_SHORT_LINE_PAD1S		BIT(24)
 #define       CSI_PP_PAD_SHORT_LINE_NOPAD		(2 << 24)
 #define       CSI_PP_EMBEDDED_DATA_EMBEDDED		BIT(20)
 #define       CSI_PP_OUTPUT_FORMAT_ARBITRARY		(0 << 16)
-#define       CSI_PP_OUTPUT_FORMAT_PIXEL		(1 << 16)
+#define       CSI_PP_OUTPUT_FORMAT_PIXEL		BIT(16)
 #define       CSI_PP_OUTPUT_FORMAT_PIXEL_REP		(2 << 16)
 #define       CSI_PP_OUTPUT_FORMAT_STORE		(3 << 16)
 #define       CSI_PP_VIRTUAL_CHANNEL_ID(n)		(((n) - 1) << 14)
@@ -214,7 +214,7 @@ enum tegra_vi_out {
 #define       CSI_A_PHY_CIL_DISABLE			0x2
 #define       CSI_A_PHY_CIL_ENABLE_MASK			0x3
 #define       CSI_B_PHY_CIL_NOP				(0x0 << 16)
-#define       CSI_B_PHY_CIL_ENABLE			(0x1 << 16)
+#define       CSI_B_PHY_CIL_ENABLE			BIT(16)
 #define       CSI_B_PHY_CIL_DISABLE			(0x2 << 16)
 #define       CSI_B_PHY_CIL_ENABLE_MASK			(0x3 << 16)
 #define TEGRA_CSI_PHY_CIL_CONTROL0(n)			(0x006c + (n) * 4)
-- 
2.53.0

Re: [PATCH] staging: media: tegra-video: use BIT() macro instead of bitwise shift

Posted by Luca Ceresoli 2 weeks, 2 days ago

Hello,

On Mon Sep 7, 2026 at 7:33 PM CEST, Lalit Shankar Chowdhury wrote:
> Replace the remaining instances of (1 << X) with BIT(X) to follow the
> kernel coding style guidelines.
>
> Signed-off-by: Lalit Shankar Chowdhury <lalitshankarch@gmail.com>
> ---
>  drivers/staging/media/tegra-video/tegra20.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/media/tegra-video/tegra20.c
> index eb1fc5b7e2cd..2586a137d9da 100644
> --- a/drivers/staging/media/tegra-video/tegra20.c
> +++ b/drivers/staging/media/tegra-video/tegra20.c
> @@ -177,15 +177,15 @@ enum tegra_vi_out {
>  #define       CSI_SKIP_PACKET_THRESHOLD(n)		(((n) & 0xff) << 16)
>  #define TEGRA_CSI_PIXEL_STREAM_CONTROL0(n)		(0x0018 + (n) * 0x2c)
>  #define       CSI_PP_PAD_FRAME_PAD0S			(0 << 28)
> -#define       CSI_PP_PAD_FRAME_PAD1S			(1 << 28)
> +#define       CSI_PP_PAD_FRAME_PAD1S			BIT(28)
>  #define       CSI_PP_PAD_FRAME_NOPAD			(2 << 28)
>  #define       CSI_PP_HEADER_EC_ENABLE			BIT(27)
>  #define       CSI_PP_PAD_SHORT_LINE_PAD0S		(0 << 24)
> -#define       CSI_PP_PAD_SHORT_LINE_PAD1S		(1 << 24)
> +#define       CSI_PP_PAD_SHORT_LINE_PAD1S		BIT(24)
>  #define       CSI_PP_PAD_SHORT_LINE_NOPAD		(2 << 24)
>  #define       CSI_PP_EMBEDDED_DATA_EMBEDDED		BIT(20)
>  #define       CSI_PP_OUTPUT_FORMAT_ARBITRARY		(0 << 16)
> -#define       CSI_PP_OUTPUT_FORMAT_PIXEL		(1 << 16)
> +#define       CSI_PP_OUTPUT_FORMAT_PIXEL		BIT(16)
>  #define       CSI_PP_OUTPUT_FORMAT_PIXEL_REP		(2 << 16)
>  #define       CSI_PP_OUTPUT_FORMAT_STORE		(3 << 16)
>  #define       CSI_PP_VIRTUAL_CHANNEL_ID(n)		(((n) - 1) << 14)
> @@ -214,7 +214,7 @@ enum tegra_vi_out {
>  #define       CSI_A_PHY_CIL_DISABLE			0x2
>  #define       CSI_A_PHY_CIL_ENABLE_MASK			0x3
>  #define       CSI_B_PHY_CIL_NOP				(0x0 << 16)
> -#define       CSI_B_PHY_CIL_ENABLE			(0x1 << 16)
> +#define       CSI_B_PHY_CIL_ENABLE			BIT(16)
>  #define       CSI_B_PHY_CIL_DISABLE			(0x2 << 16)
>  #define       CSI_B_PHY_CIL_ENABLE_MASK			(0x3 << 16)
>  #define TEGRA_CSI_PHY_CIL_CONTROL0(n)			(0x006c + (n) * 4)

The same change has been rejected multiple times. See the previous
discussions for the rationale:
https://lore.kernel.org/all/?q=s%3ABIT+dfb%3ABIT+dfn%3Adrivers%2Fstaging%2Fmedia%2Ftegra-video

If you want to improve this code, use GENMASK() or FIELD_PREP_CONST().

Luca

--
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com