arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 24 ++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-)
This SoC implements GIC600 with GICv3 ITS and PCIe host mode on this
SoC can use it. Add GIC ITS node into GIC node, update interrupt-map
and add msi-map into PCIe controller node.
The GIC ITS does have master interface to issue transactions to RAM.
The interface does support cacheable transactions, however, it does
not support shareable attribute, because the AXI port signals are tied
to inactive in this implementation. Therefore, add "dma-noncoherent"
DT property into the GIC ITS subnode.
The GIC redistributor does not have cacheable/shareable, therefore
add "dma-noncoherent" DT property into the GIC node.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 24 ++++++++++++++++++-----
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
index c66fb22d72aa8..5f9223a0f4468 100644
--- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
@@ -691,6 +691,8 @@ pciec0: pcie@e65d0000 {
resets = <&cpg 624>, <&cpg 1121>;
reset-names = "pwr", "core";
max-link-speed = <4>;
+ msi-parent = <&its 0>;
+ msi-map = <0x0 &its 0x0 0x10000>;
num-lanes = <2>;
#address-cells = <3>;
#size-cells = <2>;
@@ -701,10 +703,10 @@ pciec0: pcie@e65d0000 {
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic 0 0 GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic 0 0 GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic 0 0 GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
snps,enable-cdm-check;
status = "disabled";
};
@@ -1852,11 +1854,23 @@ ipmmu_mm: iommu@eefc0000 {
gic: interrupt-controller@f1000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
- #address-cells = <0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
interrupt-controller;
reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ dma-noncoherent;
+
+ ranges = <0x0 0x0 0x0 0xf1000000 0x0 0x200000>;
+
+ its: msi-controller@40000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x40000 0x0 0x20000>;
+ dma-noncoherent;
+ msi-controller;
+ #msi-cells = <1>;
+ };
};
csi40: csi2@fe500000 {
--
2.53.0Hi Marek,
On Sun, 6 Sept 2026 at 16:01, Marek Vasut
<marek.vasut+renesas@mailbox.org> wrote:
> This SoC implements GIC600 with GICv3 ITS and PCIe host mode on this
> SoC can use it. Add GIC ITS node into GIC node, update interrupt-map
> and add msi-map into PCIe controller node.
>
> The GIC ITS does have master interface to issue transactions to RAM.
> The interface does support cacheable transactions, however, it does
> not support shareable attribute, because the AXI port signals are tied
> to inactive in this implementation. Therefore, add "dma-noncoherent"
> DT property into the GIC ITS subnode.
>
> The GIC redistributor does not have cacheable/shareable, therefore
> add "dma-noncoherent" DT property into the GIC node.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Thanks for your patch!
As I am not PCIe DT expert, I am comparing this to the corresponding
patch for R-Car V4H, which I have already queued as commit
7fe73a3a3f2c3718 ("arm64: dts: renesas: r8a779g0: Add GICv3 ITS and
update PCIe nodes") in renesas-devel, but which probably needs some
updates.
> --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
> @@ -691,6 +691,8 @@ pciec0: pcie@e65d0000 {
> resets = <&cpg 624>, <&cpg 1121>;
> reset-names = "pwr", "core";
> max-link-speed = <4>;
> + msi-parent = <&its 0>;
This has an extra cell "0", which is probably correct, given
"#msi-cells = <1>" below.
> + msi-map = <0x0 &its 0x0 0x10000>;
This is not present on R-Car V4H (which is probably wrong).
Interestingly, Documentation/devicetree/bindings/pci/pci-ep.yaml
documents msi-map for endpoint node, so should it be added to the
pcie-ep node, too?
> num-lanes = <2>;
> #address-cells = <3>;
> #size-cells = <2>;
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On 9/8/26 10:46 AM, Geert Uytterhoeven wrote:
Hello Geert,
> As I am not PCIe DT expert, I am comparing this to the corresponding
> patch for R-Car V4H, which I have already queued as commit
> 7fe73a3a3f2c3718 ("arm64: dts: renesas: r8a779g0: Add GICv3 ITS and
> update PCIe nodes") in renesas-devel, but which probably needs some
> updates.
I sent a fix for that one:
[PATCH] arm64: dts: renesas: r8a779g0: Add MSI cells to GICv3 ITS
>> --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
>> @@ -691,6 +691,8 @@ pciec0: pcie@e65d0000 {
>> resets = <&cpg 624>, <&cpg 1121>;
>> reset-names = "pwr", "core";
>> max-link-speed = <4>;
>> + msi-parent = <&its 0>;
>
> This has an extra cell "0", which is probably correct, given
> "#msi-cells = <1>" below.
>
>> + msi-map = <0x0 &its 0x0 0x10000>;
>
> This is not present on R-Car V4H (which is probably wrong).
>
> Interestingly, Documentation/devicetree/bindings/pci/pci-ep.yaml
> documents msi-map for endpoint node, so should it be added to the
> pcie-ep node, too?
I do not think we should be adding it until we can test ITS with EP ?
This patch adds the ITS only to the RC side, where I can test it.
Hi Marek,
On Tue, 8 Sept 2026 at 18:27, Marek Vasut <marek.vasut@mailbox.org> wrote:
> On 9/8/26 10:46 AM, Geert Uytterhoeven wrote:
> > As I am not PCIe DT expert, I am comparing this to the corresponding
> > patch for R-Car V4H, which I have already queued as commit
> > 7fe73a3a3f2c3718 ("arm64: dts: renesas: r8a779g0: Add GICv3 ITS and
> > update PCIe nodes") in renesas-devel, but which probably needs some
> > updates.
>
> I sent a fix for that one:
>
> [PATCH] arm64: dts: renesas: r8a779g0: Add MSI cells to GICv3 ITS
Thanks!
> >> --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
> >> +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
> >> @@ -691,6 +691,8 @@ pciec0: pcie@e65d0000 {
> >> resets = <&cpg 624>, <&cpg 1121>;
> >> reset-names = "pwr", "core";
> >> max-link-speed = <4>;
> >> + msi-parent = <&its 0>;
> >
> > This has an extra cell "0", which is probably correct, given
> > "#msi-cells = <1>" below.
> >
> >> + msi-map = <0x0 &its 0x0 0x10000>;
> >
> > This is not present on R-Car V4H (which is probably wrong).
> >
> > Interestingly, Documentation/devicetree/bindings/pci/pci-ep.yaml
> > documents msi-map for endpoint node, so should it be added to the
> > pcie-ep node, too?
>
> I do not think we should be adding it until we can test ITS with EP ?
> This patch adds the ITS only to the RC side, where I can test it.
OK
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v7.4.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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