drivers/clk/spacemit/ccu-k3.c | 96 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+)
The K3 CPU PLL rate tables currently describe only one rate per PLL,
although the hardware supports a wider range.
PLL3 and PLL4 support rates from 1.05 to 2.4 GHz, while PLL5 and PLL8
support rates from 1.05 to 2 GHz. Populate the tables with every
supported rate in 50 MHz steps.
Cc: stable@vger.kernel.org # 7.0+
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
---
The corresponding U-Boot changes are available at:
- Add the CPU PLL rate tables:
https://github.com/spacemit-com/uboot-2022.10/commit/787b5cf44c8dbc99db886d5522c0c9cd5a96ffd6
- Correct the 1.10 GHz and 2.15 GHz table entries:
https://github.com/spacemit-com/uboot-2022.10/commit/16a775c20e9efb54ca55352215e76eb3f12e6cf0
---
Changes in v4:
- Expand the update to every supported PLL3, PLL4, PLL5 and PLL8 rate.
- Drop Aurelien Jarno's Reviewed-by and Tested-by trailers because the
patch scope has expanded.
- Add U-Boot references for the complete tables and corrected entries.
- Link to v3: https://patch.msgid.link/20260831-k3-pll5-pll8-1800mhz-v3-1-530ed0978615@linux.spacemit.com
Changes in v3:
- Mark the change for stable kernels starting with v7.0.
- Add Aurelien Jarno's Reviewed-by and Tested-by trailers.
- Rebase onto v7.3-rc1.
- Link to v2: https://patch.msgid.link/20260810-k3-pll5-pll8-1800mhz-v2-1-aabff510a797@linux.spacemit.com
Changes in v2:
- Drop "clk: spacemit: re-enable PLLs after init"; the PLL init issue
will be handled in a separate series.
- Send the K3 PLL5 and PLL8 1.8 GHz rate-table update as a standalone
patch.
- Clarify that 1.8 GHz is nominal and 2 GHz is an overclocking rate.
- Link to v1: https://patch.msgid.link/20260804-k3-pll5-pll8-1800mhz-v1-0-a3a75866ce32@linux.spacemit.com
To: Stephen Boyd <sboyd@kernel.org>
To: Brian Masney <bmasney+clk@redhat.com>
To: Jerome Brunet <jbrunet+clk@baylibre.com>
To: Yixun Lan <dlan@kernel.org>
To: Paul Walmsley <pjw@kernel.org>
To: Palmer Dabbelt <palmer@dabbelt.com>
To: Albert Ou <aou@eecs.berkeley.edu>
To: Alexandre Ghiti <alex@ghiti.fr>
Cc: linux-clk@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Cc: spacemit@lists.linux.dev
Cc: linux-kernel@vger.kernel.org
---
drivers/clk/spacemit/ccu-k3.c | 96 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c
index 92b930d5ff30..950bf531c734 100644
--- a/drivers/clk/spacemit/ccu-k3.c
+++ b/drivers/clk/spacemit/ccu-k3.c
@@ -29,15 +29,91 @@ static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = {
CCU_PLLA_RATE(3000000000UL, 0x0b3e2000, 0x00000000, 0xa0558c8c),
};
+/* Keep the firmware default as the first entry. */
static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = {
+ CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686),
+ CCU_PLLA_RATE(1050000000UL, 0x0b2b3000, 0x00000000, 0xa0458080),
+ CCU_PLLA_RATE(1100000000UL, 0x0b2d3555, 0x00005500, 0xa0458181),
+ CCU_PLLA_RATE(1150000000UL, 0x0b2f3aaa, 0x0000ab00, 0xa0458181),
+ CCU_PLLA_RATE(1200000000UL, 0x0b320000, 0x00000000, 0xa0458181),
+ CCU_PLLA_RATE(1250000000UL, 0x0b340555, 0x00005500, 0xa0458181),
+ CCU_PLLA_RATE(1300000000UL, 0x0b360aaa, 0x0000ab00, 0xa0458282),
+ CCU_PLLA_RATE(1350000000UL, 0x0b381000, 0x00000000, 0xa0458282),
+ CCU_PLLA_RATE(1400000000UL, 0x0b3a1555, 0x00005500, 0xa0458282),
+ CCU_PLLA_RATE(1450000000UL, 0x0b3c1aaa, 0x0000ab00, 0xa0458383),
+ CCU_PLLA_RATE(1500000000UL, 0x0b3e2000, 0x00000000, 0xa0458383),
+ CCU_PLLA_RATE(1550000000UL, 0x0b402555, 0x00005500, 0xa0458383),
+ CCU_PLLA_RATE(1600000000UL, 0x0b422aaa, 0x0000ab00, 0xa0458484),
+ CCU_PLLA_RATE(1650000000UL, 0x0b443000, 0x00000000, 0xa0458484),
+ CCU_PLLA_RATE(1700000000UL, 0x0b463555, 0x00005500, 0xa0458484),
+ CCU_PLLA_RATE(1750000000UL, 0x0b483aaa, 0x0000ab00, 0xa0458585),
+ CCU_PLLA_RATE(1800000000UL, 0x0b4b0000, 0x00000000, 0xa0458585),
+ CCU_PLLA_RATE(1850000000UL, 0x0b4d0555, 0x00005500, 0xa0458585),
+ CCU_PLLA_RATE(1900000000UL, 0x0b4f0aaa, 0x0000ab00, 0xa0458686),
+ CCU_PLLA_RATE(1950000000UL, 0x0b511000, 0x00000000, 0xa0458686),
+ CCU_PLLA_RATE(2050000000UL, 0x0b2a2d55, 0x00005500, 0xa0558686),
+ CCU_PLLA_RATE(2100000000UL, 0x0b2b3000, 0x00000000, 0xa0558787),
+ CCU_PLLA_RATE(2150000000UL, 0x0b2c32aa, 0x0000ab00, 0xa0558787),
CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787),
+ CCU_PLLA_RATE(2250000000UL, 0x0b2e3800, 0x00000000, 0xa0558888),
+ CCU_PLLA_RATE(2300000000UL, 0x0b2f3aaa, 0x0000ab00, 0xa0558888),
+ CCU_PLLA_RATE(2350000000UL, 0x0b303d55, 0x00005500, 0xa0558888),
+ CCU_PLLA_RATE(2400000000UL, 0x0b320000, 0x00000000, 0xa0558989),
};
+/* Keep the firmware default as the first entry. */
static const struct ccu_pll_rate_tbl pll4_rate_tbl[] = {
+ CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686),
+ CCU_PLLA_RATE(1050000000UL, 0x0b2b3000, 0x00000000, 0xa0458080),
+ CCU_PLLA_RATE(1100000000UL, 0x0b2d3555, 0x00005500, 0xa0458181),
+ CCU_PLLA_RATE(1150000000UL, 0x0b2f3aaa, 0x0000ab00, 0xa0458181),
+ CCU_PLLA_RATE(1200000000UL, 0x0b320000, 0x00000000, 0xa0458181),
+ CCU_PLLA_RATE(1250000000UL, 0x0b340555, 0x00005500, 0xa0458181),
+ CCU_PLLA_RATE(1300000000UL, 0x0b360aaa, 0x0000ab00, 0xa0458282),
+ CCU_PLLA_RATE(1350000000UL, 0x0b381000, 0x00000000, 0xa0458282),
+ CCU_PLLA_RATE(1400000000UL, 0x0b3a1555, 0x00005500, 0xa0458282),
+ CCU_PLLA_RATE(1450000000UL, 0x0b3c1aaa, 0x0000ab00, 0xa0458383),
+ CCU_PLLA_RATE(1500000000UL, 0x0b3e2000, 0x00000000, 0xa0458383),
+ CCU_PLLA_RATE(1550000000UL, 0x0b402555, 0x00005500, 0xa0458383),
+ CCU_PLLA_RATE(1600000000UL, 0x0b422aaa, 0x0000ab00, 0xa0458484),
+ CCU_PLLA_RATE(1650000000UL, 0x0b443000, 0x00000000, 0xa0458484),
+ CCU_PLLA_RATE(1700000000UL, 0x0b463555, 0x00005500, 0xa0458484),
+ CCU_PLLA_RATE(1750000000UL, 0x0b483aaa, 0x0000ab00, 0xa0458585),
+ CCU_PLLA_RATE(1800000000UL, 0x0b4b0000, 0x00000000, 0xa0458585),
+ CCU_PLLA_RATE(1850000000UL, 0x0b4d0555, 0x00005500, 0xa0458585),
+ CCU_PLLA_RATE(1900000000UL, 0x0b4f0aaa, 0x0000ab00, 0xa0458686),
+ CCU_PLLA_RATE(1950000000UL, 0x0b511000, 0x00000000, 0xa0458686),
+ CCU_PLLA_RATE(2050000000UL, 0x0b2a2d55, 0x00005500, 0xa0558686),
+ CCU_PLLA_RATE(2100000000UL, 0x0b2b3000, 0x00000000, 0xa0558787),
+ CCU_PLLA_RATE(2150000000UL, 0x0b2c32aa, 0x0000ab00, 0xa0558787),
CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787),
+ CCU_PLLA_RATE(2250000000UL, 0x0b2e3800, 0x00000000, 0xa0558888),
+ CCU_PLLA_RATE(2300000000UL, 0x0b2f3aaa, 0x0000ab00, 0xa0558888),
+ CCU_PLLA_RATE(2350000000UL, 0x0b303d55, 0x00005500, 0xa0558888),
+ CCU_PLLA_RATE(2400000000UL, 0x0b320000, 0x00000000, 0xa0558989),
};
+/* Keep the firmware default as the first entry. */
static const struct ccu_pll_rate_tbl pll5_rate_tbl[] = {
+ CCU_PLLA_RATE(1800000000UL, 0x0b4b0000, 0x00000000, 0xa0458585),
+ CCU_PLLA_RATE(1050000000UL, 0x0b2b3000, 0x00000000, 0xa0458080),
+ CCU_PLLA_RATE(1100000000UL, 0x0b2d3555, 0x00005500, 0xa0458181),
+ CCU_PLLA_RATE(1150000000UL, 0x0b2f3aaa, 0x0000ab00, 0xa0458181),
+ CCU_PLLA_RATE(1200000000UL, 0x0b320000, 0x00000000, 0xa0458181),
+ CCU_PLLA_RATE(1250000000UL, 0x0b340555, 0x00005500, 0xa0458181),
+ CCU_PLLA_RATE(1300000000UL, 0x0b360aaa, 0x0000ab00, 0xa0458282),
+ CCU_PLLA_RATE(1350000000UL, 0x0b381000, 0x00000000, 0xa0458282),
+ CCU_PLLA_RATE(1400000000UL, 0x0b3a1555, 0x00005500, 0xa0458282),
+ CCU_PLLA_RATE(1450000000UL, 0x0b3c1aaa, 0x0000ab00, 0xa0458383),
+ CCU_PLLA_RATE(1500000000UL, 0x0b3e2000, 0x00000000, 0xa0458383),
+ CCU_PLLA_RATE(1550000000UL, 0x0b402555, 0x00005500, 0xa0458383),
+ CCU_PLLA_RATE(1600000000UL, 0x0b422aaa, 0x0000ab00, 0xa0458484),
+ CCU_PLLA_RATE(1650000000UL, 0x0b443000, 0x00000000, 0xa0458484),
+ CCU_PLLA_RATE(1700000000UL, 0x0b463555, 0x00005500, 0xa0458484),
+ CCU_PLLA_RATE(1750000000UL, 0x0b483aaa, 0x0000ab00, 0xa0458585),
+ CCU_PLLA_RATE(1850000000UL, 0x0b4d0555, 0x00005500, 0xa0458585),
+ CCU_PLLA_RATE(1900000000UL, 0x0b4f0aaa, 0x0000ab00, 0xa0458686),
+ CCU_PLLA_RATE(1950000000UL, 0x0b511000, 0x00000000, 0xa0458686),
CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686),
};
@@ -49,7 +125,27 @@ static const struct ccu_pll_rate_tbl pll7_rate_tbl[] = {
CCU_PLLA_RATE(2800000000UL, 0x0b3a1555, 0x00005500, 0xa0558b8b),
};
+/* Keep the firmware default as the first entry. */
static const struct ccu_pll_rate_tbl pll8_rate_tbl[] = {
+ CCU_PLLA_RATE(1800000000UL, 0x0b4b0000, 0x00000000, 0xa0458585),
+ CCU_PLLA_RATE(1050000000UL, 0x0b2b3000, 0x00000000, 0xa0458080),
+ CCU_PLLA_RATE(1100000000UL, 0x0b2d3555, 0x00005500, 0xa0458181),
+ CCU_PLLA_RATE(1150000000UL, 0x0b2f3aaa, 0x0000ab00, 0xa0458181),
+ CCU_PLLA_RATE(1200000000UL, 0x0b320000, 0x00000000, 0xa0458181),
+ CCU_PLLA_RATE(1250000000UL, 0x0b340555, 0x00005500, 0xa0458181),
+ CCU_PLLA_RATE(1300000000UL, 0x0b360aaa, 0x0000ab00, 0xa0458282),
+ CCU_PLLA_RATE(1350000000UL, 0x0b381000, 0x00000000, 0xa0458282),
+ CCU_PLLA_RATE(1400000000UL, 0x0b3a1555, 0x00005500, 0xa0458282),
+ CCU_PLLA_RATE(1450000000UL, 0x0b3c1aaa, 0x0000ab00, 0xa0458383),
+ CCU_PLLA_RATE(1500000000UL, 0x0b3e2000, 0x00000000, 0xa0458383),
+ CCU_PLLA_RATE(1550000000UL, 0x0b402555, 0x00005500, 0xa0458383),
+ CCU_PLLA_RATE(1600000000UL, 0x0b422aaa, 0x0000ab00, 0xa0458484),
+ CCU_PLLA_RATE(1650000000UL, 0x0b443000, 0x00000000, 0xa0458484),
+ CCU_PLLA_RATE(1700000000UL, 0x0b463555, 0x00005500, 0xa0458484),
+ CCU_PLLA_RATE(1750000000UL, 0x0b483aaa, 0x0000ab00, 0xa0458585),
+ CCU_PLLA_RATE(1850000000UL, 0x0b4d0555, 0x00005500, 0xa0458585),
+ CCU_PLLA_RATE(1900000000UL, 0x0b4f0aaa, 0x0000ab00, 0xa0458686),
+ CCU_PLLA_RATE(1950000000UL, 0x0b511000, 0x00000000, 0xa0458686),
CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686),
};
---
base-commit: cee9395acd8043be0644b25c34bfa86623f2b935
change-id: 20260802-k3-pll5-pll8-1800mhz-c81875a0a944
Best regards,
--
Troy Mitchell <troy.mitchell@linux.spacemit.com>Hi Troy, On Thu, Sep 03, 2026 at 11:06:24AM +0800, Troy Mitchell wrote: > The K3 CPU PLL rate tables currently describe only one rate per PLL, > although the hardware supports a wider range. > > PLL3 and PLL4 support rates from 1.05 to 2.4 GHz, while PLL5 and PLL8 > support rates from 1.05 to 2 GHz. Populate the tables with every > supported rate in 50 MHz steps. > > Cc: stable@vger.kernel.org # 7.0+ > Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> > --- > The corresponding U-Boot changes are available at: > > - Add the CPU PLL rate tables: > https://github.com/spacemit-com/uboot-2022.10/commit/787b5cf44c8dbc99db886d5522c0c9cd5a96ffd6 > - Correct the 1.10 GHz and 2.15 GHz table entries: > https://github.com/spacemit-com/uboot-2022.10/commit/16a775c20e9efb54ca55352215e76eb3f12e6cf0 > --- > Changes in v4: > - Expand the update to every supported PLL3, PLL4, PLL5 and PLL8 rate. > - Drop Aurelien Jarno's Reviewed-by and Tested-by trailers because the > patch scope has expanded. > - Add U-Boot references for the complete tables and corrected entries. > - Link to v3: https://patch.msgid.link/20260831-k3-pll5-pll8-1800mhz-v3-1-530ed0978615@linux.spacemit.com > > Changes in v3: > - Mark the change for stable kernels starting with v7.0. > - Add Aurelien Jarno's Reviewed-by and Tested-by trailers. > - Rebase onto v7.3-rc1. > - Link to v2: https://patch.msgid.link/20260810-k3-pll5-pll8-1800mhz-v2-1-aabff510a797@linux.spacemit.com > > Changes in v2: > - Drop "clk: spacemit: re-enable PLLs after init"; the PLL init issue > will be handled in a separate series. > - Send the K3 PLL5 and PLL8 1.8 GHz rate-table update as a standalone > patch. > - Clarify that 1.8 GHz is nominal and 2 GHz is an overclocking rate. > - Link to v1: https://patch.msgid.link/20260804-k3-pll5-pll8-1800mhz-v1-0-a3a75866ce32@linux.spacemit.com > > To: Stephen Boyd <sboyd@kernel.org> > To: Brian Masney <bmasney+clk@redhat.com> > To: Jerome Brunet <jbrunet+clk@baylibre.com> > To: Yixun Lan <dlan@kernel.org> > To: Paul Walmsley <pjw@kernel.org> > To: Palmer Dabbelt <palmer@dabbelt.com> > To: Albert Ou <aou@eecs.berkeley.edu> > To: Alexandre Ghiti <alex@ghiti.fr> > Cc: linux-clk@vger.kernel.org > Cc: linux-riscv@lists.infradead.org > Cc: spacemit@lists.linux.dev > Cc: linux-kernel@vger.kernel.org > --- > drivers/clk/spacemit/ccu-k3.c | 96 +++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 96 insertions(+) > On a recently new K3 board (shipped with OpenSBI/U-boot dated end of July), I was seeing upstream kernel boot hang after IMSIC initialization. Some logging indicated that it was hanging around the clock controller initializations (k3_ccu_driver_init). On a board running older U-boot/OpenSBI from May, I originally didn't observe this hang, but doing multiple repeated boots showed a rare instance of this hang happening. Some changes were added to OpenSBI in this period (end of June) that trap clock controller registers to M Mode and handle reads/writes there. Yixun pointed me to this patch, and it seems to fix the boot hang on the board runner newer OpenSBI. I think this avoids some kind of a race condition with disabling/re-enabling a PLL that the clock driver does. I'm finding it a bit hard to explain/understand what exactly it the reason though. Yixun, could this patch get added in soon? Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> Regards Anirudh Srinivasan
Hi Anirudh, On 11:41 Sat 05 Sep , Anirudh Srinivasan wrote: > Hi Troy, > .. > > drivers/clk/spacemit/ccu-k3.c | 96 +++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 96 insertions(+) > > > > On a recently new K3 board (shipped with OpenSBI/U-boot dated > end of July), I was seeing upstream kernel boot hang after IMSIC > initialization. Some logging indicated that it was hanging around the > clock controller initializations (k3_ccu_driver_init). > > On a board running older U-boot/OpenSBI from May, I originally didn't > observe this hang, but doing multiple repeated boots showed a rare > instance of this hang happening. Some changes were added to OpenSBI in > this period (end of June) that trap clock controller registers to M > Mode and handle reads/writes there. > > Yixun pointed me to this patch, and it seems to fix the boot hang on > the board runner newer OpenSBI. I think this avoids some kind of a > race condition with disabling/re-enabling a PLL that the clock driver > does. I'm finding it a bit hard to explain/understand what exactly it > the reason though. > .. > Yixun, could this patch get added in soon? > Let's wait a bit, the patch itself do solve the problem, but Aurelien and me still have some minor concern, see other post in this thread Although the problem is a combination of vendor firmware + upstream kernel, but it will affect quite widely and probably last for quite long time, so I think it would warrant a Fix tag and back port to old stable versions.. > Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> > Thanks for the testing -- Yixun Lan (dlan)
Hi Troy,
On 2026-09-03 11:06, Troy Mitchell wrote:
> The K3 CPU PLL rate tables currently describe only one rate per PLL,
> although the hardware supports a wider range.
>
> PLL3 and PLL4 support rates from 1.05 to 2.4 GHz, while PLL5 and PLL8
> support rates from 1.05 to 2 GHz. Populate the tables with every
> supported rate in 50 MHz steps.
>
> Cc: stable@vger.kernel.org # 7.0+
> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
> ---
> The corresponding U-Boot changes are available at:
>
> - Add the CPU PLL rate tables:
> https://github.com/spacemit-com/uboot-2022.10/commit/787b5cf44c8dbc99db886d5522c0c9cd5a96ffd6
> - Correct the 1.10 GHz and 2.15 GHz table entries:
> https://github.com/spacemit-com/uboot-2022.10/commit/16a775c20e9efb54ca55352215e76eb3f12e6cf0
> ---
> Changes in v4:
> - Expand the update to every supported PLL3, PLL4, PLL5 and PLL8 rate.
> - Drop Aurelien Jarno's Reviewed-by and Tested-by trailers because the
> patch scope has expanded.
> - Add U-Boot references for the complete tables and corrected entries.
> - Link to v3: https://patch.msgid.link/20260831-k3-pll5-pll8-1800mhz-v3-1-530ed0978615@linux.spacemit.com
>
> Changes in v3:
> - Mark the change for stable kernels starting with v7.0.
> - Add Aurelien Jarno's Reviewed-by and Tested-by trailers.
> - Rebase onto v7.3-rc1.
> - Link to v2: https://patch.msgid.link/20260810-k3-pll5-pll8-1800mhz-v2-1-aabff510a797@linux.spacemit.com
>
> Changes in v2:
> - Drop "clk: spacemit: re-enable PLLs after init"; the PLL init issue
> will be handled in a separate series.
> - Send the K3 PLL5 and PLL8 1.8 GHz rate-table update as a standalone
> patch.
> - Clarify that 1.8 GHz is nominal and 2 GHz is an overclocking rate.
> - Link to v1: https://patch.msgid.link/20260804-k3-pll5-pll8-1800mhz-v1-0-a3a75866ce32@linux.spacemit.com
>
> To: Stephen Boyd <sboyd@kernel.org>
> To: Brian Masney <bmasney+clk@redhat.com>
> To: Jerome Brunet <jbrunet+clk@baylibre.com>
> To: Yixun Lan <dlan@kernel.org>
> To: Paul Walmsley <pjw@kernel.org>
> To: Palmer Dabbelt <palmer@dabbelt.com>
> To: Albert Ou <aou@eecs.berkeley.edu>
> To: Alexandre Ghiti <alex@ghiti.fr>
> Cc: linux-clk@vger.kernel.org
> Cc: linux-riscv@lists.infradead.org
> Cc: spacemit@lists.linux.dev
> Cc: linux-kernel@vger.kernel.org
> ---
> drivers/clk/spacemit/ccu-k3.c | 96 +++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
Thanks for the patch, it makes sense to add all the values, to support
future firmware changes. The values match the ones in the vendor kernel.
> diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c
> index 92b930d5ff30..950bf531c734 100644
> --- a/drivers/clk/spacemit/ccu-k3.c
> +++ b/drivers/clk/spacemit/ccu-k3.c
> @@ -29,15 +29,91 @@ static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = {
> CCU_PLLA_RATE(3000000000UL, 0x0b3e2000, 0x00000000, 0xa0558c8c),
> };
>
> +/* Keep the firmware default as the first entry. */
> static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = {
> + CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686),
Is it really necessary to put this entry first? I guess it's the current
default frequency, but we have seen it can evolve. From my tests, the
driver seems to just keep the value configured by the firmware
independently from the table order, so I am not sure it's necessary.
> + CCU_PLLA_RATE(1050000000UL, 0x0b2b3000, 0x00000000, 0xa0458080),
> + CCU_PLLA_RATE(1100000000UL, 0x0b2d3555, 0x00005500, 0xa0458181),
> + CCU_PLLA_RATE(1150000000UL, 0x0b2f3aaa, 0x0000ab00, 0xa0458181),
> + CCU_PLLA_RATE(1200000000UL, 0x0b320000, 0x00000000, 0xa0458181),
> + CCU_PLLA_RATE(1250000000UL, 0x0b340555, 0x00005500, 0xa0458181),
> + CCU_PLLA_RATE(1300000000UL, 0x0b360aaa, 0x0000ab00, 0xa0458282),
> + CCU_PLLA_RATE(1350000000UL, 0x0b381000, 0x00000000, 0xa0458282),
> + CCU_PLLA_RATE(1400000000UL, 0x0b3a1555, 0x00005500, 0xa0458282),
> + CCU_PLLA_RATE(1450000000UL, 0x0b3c1aaa, 0x0000ab00, 0xa0458383),
> + CCU_PLLA_RATE(1500000000UL, 0x0b3e2000, 0x00000000, 0xa0458383),
> + CCU_PLLA_RATE(1550000000UL, 0x0b402555, 0x00005500, 0xa0458383),
> + CCU_PLLA_RATE(1600000000UL, 0x0b422aaa, 0x0000ab00, 0xa0458484),
> + CCU_PLLA_RATE(1650000000UL, 0x0b443000, 0x00000000, 0xa0458484),
> + CCU_PLLA_RATE(1700000000UL, 0x0b463555, 0x00005500, 0xa0458484),
> + CCU_PLLA_RATE(1750000000UL, 0x0b483aaa, 0x0000ab00, 0xa0458585),
> + CCU_PLLA_RATE(1800000000UL, 0x0b4b0000, 0x00000000, 0xa0458585),
> + CCU_PLLA_RATE(1850000000UL, 0x0b4d0555, 0x00005500, 0xa0458585),
> + CCU_PLLA_RATE(1900000000UL, 0x0b4f0aaa, 0x0000ab00, 0xa0458686),
> + CCU_PLLA_RATE(1950000000UL, 0x0b511000, 0x00000000, 0xa0458686),
> + CCU_PLLA_RATE(2050000000UL, 0x0b2a2d55, 0x00005500, 0xa0558686),
> + CCU_PLLA_RATE(2100000000UL, 0x0b2b3000, 0x00000000, 0xa0558787),
> + CCU_PLLA_RATE(2150000000UL, 0x0b2c32aa, 0x0000ab00, 0xa0558787),
> CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787),
> + CCU_PLLA_RATE(2250000000UL, 0x0b2e3800, 0x00000000, 0xa0558888),
> + CCU_PLLA_RATE(2300000000UL, 0x0b2f3aaa, 0x0000ab00, 0xa0558888),
> + CCU_PLLA_RATE(2350000000UL, 0x0b303d55, 0x00005500, 0xa0558888),
> + CCU_PLLA_RATE(2400000000UL, 0x0b320000, 0x00000000, 0xa0558989),
> };
>
> +/* Keep the firmware default as the first entry. */
> static const struct ccu_pll_rate_tbl pll4_rate_tbl[] = {
> + CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686),
> + CCU_PLLA_RATE(1050000000UL, 0x0b2b3000, 0x00000000, 0xa0458080),
> + CCU_PLLA_RATE(1100000000UL, 0x0b2d3555, 0x00005500, 0xa0458181),
> + CCU_PLLA_RATE(1150000000UL, 0x0b2f3aaa, 0x0000ab00, 0xa0458181),
> + CCU_PLLA_RATE(1200000000UL, 0x0b320000, 0x00000000, 0xa0458181),
> + CCU_PLLA_RATE(1250000000UL, 0x0b340555, 0x00005500, 0xa0458181),
> + CCU_PLLA_RATE(1300000000UL, 0x0b360aaa, 0x0000ab00, 0xa0458282),
> + CCU_PLLA_RATE(1350000000UL, 0x0b381000, 0x00000000, 0xa0458282),
> + CCU_PLLA_RATE(1400000000UL, 0x0b3a1555, 0x00005500, 0xa0458282),
> + CCU_PLLA_RATE(1450000000UL, 0x0b3c1aaa, 0x0000ab00, 0xa0458383),
> + CCU_PLLA_RATE(1500000000UL, 0x0b3e2000, 0x00000000, 0xa0458383),
> + CCU_PLLA_RATE(1550000000UL, 0x0b402555, 0x00005500, 0xa0458383),
> + CCU_PLLA_RATE(1600000000UL, 0x0b422aaa, 0x0000ab00, 0xa0458484),
> + CCU_PLLA_RATE(1650000000UL, 0x0b443000, 0x00000000, 0xa0458484),
> + CCU_PLLA_RATE(1700000000UL, 0x0b463555, 0x00005500, 0xa0458484),
> + CCU_PLLA_RATE(1750000000UL, 0x0b483aaa, 0x0000ab00, 0xa0458585),
> + CCU_PLLA_RATE(1800000000UL, 0x0b4b0000, 0x00000000, 0xa0458585),
> + CCU_PLLA_RATE(1850000000UL, 0x0b4d0555, 0x00005500, 0xa0458585),
> + CCU_PLLA_RATE(1900000000UL, 0x0b4f0aaa, 0x0000ab00, 0xa0458686),
> + CCU_PLLA_RATE(1950000000UL, 0x0b511000, 0x00000000, 0xa0458686),
> + CCU_PLLA_RATE(2050000000UL, 0x0b2a2d55, 0x00005500, 0xa0558686),
> + CCU_PLLA_RATE(2100000000UL, 0x0b2b3000, 0x00000000, 0xa0558787),
> + CCU_PLLA_RATE(2150000000UL, 0x0b2c32aa, 0x0000ab00, 0xa0558787),
> CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787),
> + CCU_PLLA_RATE(2250000000UL, 0x0b2e3800, 0x00000000, 0xa0558888),
> + CCU_PLLA_RATE(2300000000UL, 0x0b2f3aaa, 0x0000ab00, 0xa0558888),
> + CCU_PLLA_RATE(2350000000UL, 0x0b303d55, 0x00005500, 0xa0558888),
> + CCU_PLLA_RATE(2400000000UL, 0x0b320000, 0x00000000, 0xa0558989),
> };
>
> +/* Keep the firmware default as the first entry. */
> static const struct ccu_pll_rate_tbl pll5_rate_tbl[] = {
> + CCU_PLLA_RATE(1800000000UL, 0x0b4b0000, 0x00000000, 0xa0458585),
Ditto
> + CCU_PLLA_RATE(1050000000UL, 0x0b2b3000, 0x00000000, 0xa0458080),
> + CCU_PLLA_RATE(1100000000UL, 0x0b2d3555, 0x00005500, 0xa0458181),
> + CCU_PLLA_RATE(1150000000UL, 0x0b2f3aaa, 0x0000ab00, 0xa0458181),
> + CCU_PLLA_RATE(1200000000UL, 0x0b320000, 0x00000000, 0xa0458181),
> + CCU_PLLA_RATE(1250000000UL, 0x0b340555, 0x00005500, 0xa0458181),
> + CCU_PLLA_RATE(1300000000UL, 0x0b360aaa, 0x0000ab00, 0xa0458282),
> + CCU_PLLA_RATE(1350000000UL, 0x0b381000, 0x00000000, 0xa0458282),
> + CCU_PLLA_RATE(1400000000UL, 0x0b3a1555, 0x00005500, 0xa0458282),
> + CCU_PLLA_RATE(1450000000UL, 0x0b3c1aaa, 0x0000ab00, 0xa0458383),
> + CCU_PLLA_RATE(1500000000UL, 0x0b3e2000, 0x00000000, 0xa0458383),
> + CCU_PLLA_RATE(1550000000UL, 0x0b402555, 0x00005500, 0xa0458383),
> + CCU_PLLA_RATE(1600000000UL, 0x0b422aaa, 0x0000ab00, 0xa0458484),
> + CCU_PLLA_RATE(1650000000UL, 0x0b443000, 0x00000000, 0xa0458484),
> + CCU_PLLA_RATE(1700000000UL, 0x0b463555, 0x00005500, 0xa0458484),
> + CCU_PLLA_RATE(1750000000UL, 0x0b483aaa, 0x0000ab00, 0xa0458585),
> + CCU_PLLA_RATE(1850000000UL, 0x0b4d0555, 0x00005500, 0xa0458585),
> + CCU_PLLA_RATE(1900000000UL, 0x0b4f0aaa, 0x0000ab00, 0xa0458686),
> + CCU_PLLA_RATE(1950000000UL, 0x0b511000, 0x00000000, 0xa0458686),
> CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686),
> };
>
> @@ -49,7 +125,27 @@ static const struct ccu_pll_rate_tbl pll7_rate_tbl[] = {
> CCU_PLLA_RATE(2800000000UL, 0x0b3a1555, 0x00005500, 0xa0558b8b),
> };
>
> +/* Keep the firmware default as the first entry. */
> static const struct ccu_pll_rate_tbl pll8_rate_tbl[] = {
> + CCU_PLLA_RATE(1800000000UL, 0x0b4b0000, 0x00000000, 0xa0458585),
> + CCU_PLLA_RATE(1050000000UL, 0x0b2b3000, 0x00000000, 0xa0458080),
> + CCU_PLLA_RATE(1100000000UL, 0x0b2d3555, 0x00005500, 0xa0458181),
> + CCU_PLLA_RATE(1150000000UL, 0x0b2f3aaa, 0x0000ab00, 0xa0458181),
> + CCU_PLLA_RATE(1200000000UL, 0x0b320000, 0x00000000, 0xa0458181),
> + CCU_PLLA_RATE(1250000000UL, 0x0b340555, 0x00005500, 0xa0458181),
> + CCU_PLLA_RATE(1300000000UL, 0x0b360aaa, 0x0000ab00, 0xa0458282),
> + CCU_PLLA_RATE(1350000000UL, 0x0b381000, 0x00000000, 0xa0458282),
> + CCU_PLLA_RATE(1400000000UL, 0x0b3a1555, 0x00005500, 0xa0458282),
> + CCU_PLLA_RATE(1450000000UL, 0x0b3c1aaa, 0x0000ab00, 0xa0458383),
> + CCU_PLLA_RATE(1500000000UL, 0x0b3e2000, 0x00000000, 0xa0458383),
> + CCU_PLLA_RATE(1550000000UL, 0x0b402555, 0x00005500, 0xa0458383),
> + CCU_PLLA_RATE(1600000000UL, 0x0b422aaa, 0x0000ab00, 0xa0458484),
> + CCU_PLLA_RATE(1650000000UL, 0x0b443000, 0x00000000, 0xa0458484),
> + CCU_PLLA_RATE(1700000000UL, 0x0b463555, 0x00005500, 0xa0458484),
> + CCU_PLLA_RATE(1750000000UL, 0x0b483aaa, 0x0000ab00, 0xa0458585),
> + CCU_PLLA_RATE(1850000000UL, 0x0b4d0555, 0x00005500, 0xa0458585),
> + CCU_PLLA_RATE(1900000000UL, 0x0b4f0aaa, 0x0000ab00, 0xa0458686),
> + CCU_PLLA_RATE(1950000000UL, 0x0b511000, 0x00000000, 0xa0458686),
> CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686),
> };
I have tested the patch, and I confirm it fixes the boot hang with newer
firmware, and will fix it if the default firmware values change again.
My comments are just minor ones, so:
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Regards
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://aurel32.net
Hi Aurelien,
On Fri Sep 4, 2026 at 1:27 AM +08, Aurelien Jarno wrote:
> Hi Troy,
>
> On 2026-09-03 11:06, Troy Mitchell wrote:
>> The K3 CPU PLL rate tables currently describe only one rate per PLL,
>> although the hardware supports a wider range.
>>
>> PLL3 and PLL4 support rates from 1.05 to 2.4 GHz, while PLL5 and PLL8
>> support rates from 1.05 to 2 GHz. Populate the tables with every
>> supported rate in 50 MHz steps.
>>
>> Cc: stable@vger.kernel.org # 7.0+
>> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
>> ---
>> The corresponding U-Boot changes are available at:
>>
>> - Add the CPU PLL rate tables:
>> https://github.com/spacemit-com/uboot-2022.10/commit/787b5cf44c8dbc99db886d5522c0c9cd5a96ffd6
>> - Correct the 1.10 GHz and 2.15 GHz table entries:
>> https://github.com/spacemit-com/uboot-2022.10/commit/16a775c20e9efb54ca55352215e76eb3f12e6cf0
>> ---
>> Changes in v4:
>> - Expand the update to every supported PLL3, PLL4, PLL5 and PLL8 rate.
>> - Drop Aurelien Jarno's Reviewed-by and Tested-by trailers because the
>> patch scope has expanded.
>> - Add U-Boot references for the complete tables and corrected entries.
>> - Link to v3: https://patch.msgid.link/20260831-k3-pll5-pll8-1800mhz-v3-1-530ed0978615@linux.spacemit.com
>>
>> Changes in v3:
>> - Mark the change for stable kernels starting with v7.0.
>> - Add Aurelien Jarno's Reviewed-by and Tested-by trailers.
>> - Rebase onto v7.3-rc1.
>> - Link to v2: https://patch.msgid.link/20260810-k3-pll5-pll8-1800mhz-v2-1-aabff510a797@linux.spacemit.com
>>
>> Changes in v2:
>> - Drop "clk: spacemit: re-enable PLLs after init"; the PLL init issue
>> will be handled in a separate series.
>> - Send the K3 PLL5 and PLL8 1.8 GHz rate-table update as a standalone
>> patch.
>> - Clarify that 1.8 GHz is nominal and 2 GHz is an overclocking rate.
>> - Link to v1: https://patch.msgid.link/20260804-k3-pll5-pll8-1800mhz-v1-0-a3a75866ce32@linux.spacemit.com
>>
>> To: Stephen Boyd <sboyd@kernel.org>
>> To: Brian Masney <bmasney+clk@redhat.com>
>> To: Jerome Brunet <jbrunet+clk@baylibre.com>
>> To: Yixun Lan <dlan@kernel.org>
>> To: Paul Walmsley <pjw@kernel.org>
>> To: Palmer Dabbelt <palmer@dabbelt.com>
>> To: Albert Ou <aou@eecs.berkeley.edu>
>> To: Alexandre Ghiti <alex@ghiti.fr>
>> Cc: linux-clk@vger.kernel.org
>> Cc: linux-riscv@lists.infradead.org
>> Cc: spacemit@lists.linux.dev
>> Cc: linux-kernel@vger.kernel.org
>> ---
>> drivers/clk/spacemit/ccu-k3.c | 96 +++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 96 insertions(+)
>
> Thanks for the patch, it makes sense to add all the values, to support
> future firmware changes. The values match the ones in the vendor kernel.
I forgot that you had a similar patch as well..
>
>> diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c
>> index 92b930d5ff30..950bf531c734 100644
>> --- a/drivers/clk/spacemit/ccu-k3.c
>> +++ b/drivers/clk/spacemit/ccu-k3.c
>> @@ -29,15 +29,91 @@ static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = {
>> CCU_PLLA_RATE(3000000000UL, 0x0b3e2000, 0x00000000, 0xa0558c8c),
>> };
>>
>> +/* Keep the firmware default as the first entry. */
>> static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = {
>> + CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686),
>
> Is it really necessary to put this entry first? I guess it's the current
> default frequency, but we have seen it can evolve. From my tests, the
> driver seems to just keep the value configured by the firmware
> independently from the table order, so I am not sure it's necessary.
I think keeping it first is necessary. If the current register settings do
not match any entry in the table, ccu_plla_init() falls back to the first
entry:
ccu_plla_update_param(pll, &pll->config.rate_tbl[0]);
[...]
>> };
>
> I have tested the patch, and I confirm it fixes the boot hang with newer
> firmware, and will fix it if the default firmware values change again.
> My comments are just minor ones, so:
>
> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
> Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Thanks for the tags.
>
> Regards
> Aurelien
--
Troy Mitchell
Hi Aurelien, Troy,
On 11:24 Fri 04 Sep , Troy Mitchell wrote:
> Hi Aurelien,
>
> On Fri Sep 4, 2026 at 1:27 AM +08, Aurelien Jarno wrote:
> > Hi Troy,
> >
..
> >> drivers/clk/spacemit/ccu-k3.c | 96 +++++++++++++++++++++++++++++++++++++++++++
> >> 1 file changed, 96 insertions(+)
> >
> > Thanks for the patch, it makes sense to add all the values, to support
> > future firmware changes. The values match the ones in the vendor kernel.
> I forgot that you had a similar patch as well..
>
> >
> >> diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c
> >> index 92b930d5ff30..950bf531c734 100644
> >> --- a/drivers/clk/spacemit/ccu-k3.c
> >> +++ b/drivers/clk/spacemit/ccu-k3.c
> >> @@ -29,15 +29,91 @@ static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = {
> >> CCU_PLLA_RATE(3000000000UL, 0x0b3e2000, 0x00000000, 0xa0558c8c),
> >> };
> >>
> >> +/* Keep the firmware default as the first entry. */
> >> static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = {
> >> + CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686),
> >
> > Is it really necessary to put this entry first? I guess it's the current
> > default frequency, but we have seen it can evolve. From my tests, the
> > driver seems to just keep the value configured by the firmware
> > independently from the table order, so I am not sure it's necessary.
I agree with Aurelien here, the default frequency isn't a solid stable settings,
which it may changes in the future
> I think keeping it first is necessary. If the current register settings do
> not match any entry in the table, ccu_plla_init() falls back to the first
Isn't it a bug if all frequencies added still couldn't cover all settings?
I'd simply suggest to bail out and yell loudly if there is a mismatch
I just don't like putting specific frequency at first one as default,
this logic is kind of fragile and tend to fail easily..
> entry:
>
>
> ccu_plla_update_param(pll, &pll->config.rate_tbl[0]);
>
--
Yixun Lan (dlan)
Hi Yixun, Aurelien
On Sun Sep 6, 2026 at 6:07 AM +08, Yixun Lan wrote:
> Hi Aurelien, Troy,
>
> On 11:24 Fri 04 Sep , Troy Mitchell wrote:
>> Hi Aurelien,
>>
>> On Fri Sep 4, 2026 at 1:27 AM +08, Aurelien Jarno wrote:
>> > Hi Troy,
>> >
> ..
>> >> drivers/clk/spacemit/ccu-k3.c | 96 +++++++++++++++++++++++++++++++++++++++++++
>> >> 1 file changed, 96 insertions(+)
>> >
>> > Thanks for the patch, it makes sense to add all the values, to support
>> > future firmware changes. The values match the ones in the vendor kernel.
>> I forgot that you had a similar patch as well..
>>
>> >
>> >> diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c
>> >> index 92b930d5ff30..950bf531c734 100644
>> >> --- a/drivers/clk/spacemit/ccu-k3.c
>> >> +++ b/drivers/clk/spacemit/ccu-k3.c
>> >> @@ -29,15 +29,91 @@ static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = {
>> >> CCU_PLLA_RATE(3000000000UL, 0x0b3e2000, 0x00000000, 0xa0558c8c),
>> >> };
>> >>
>> >> +/* Keep the firmware default as the first entry. */
>> >> static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = {
>> >> + CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686),
>> >
>> > Is it really necessary to put this entry first? I guess it's the current
>> > default frequency, but we have seen it can evolve. From my tests, the
>> > driver seems to just keep the value configured by the firmware
>> > independently from the table order, so I am not sure it's necessary.
>
> I agree with Aurelien here, the default frequency isn't a solid stable settings,
> which it may changes in the future
>
>> I think keeping it first is necessary. If the current register settings do
>> not match any entry in the table, ccu_plla_init() falls back to the first
>
> Isn't it a bug if all frequencies added still couldn't cover all settings?
> I'd simply suggest to bail out and yell loudly if there is a mismatch
>
> I just don't like putting specific frequency at first one as default,
> this logic is kind of fragile and tend to fail easily..
I checked the Rockchip PLL driver. The RK3036, RK3066 and RK3399
implementations calculate the current rate directly from the hardware
register parameters. If that rate is absent from the rate table, their PLL
init callbacks return without reprogramming the PLL. With
ROCKCHIP_PLL_SYNC_RATE enabled, they only synchronize the parameters when
the current rate matches a table entry but the register parameters differ
from those in that entry.
This approach seems preferable to me. Would it make sense to sort the rate
tables by frequency in the next revision, and follow up with a separate
series to calculate the current rate from the registers and preserve
configurations whose rates are absent from the table, as Rockchip does?
>
>> entry:
>>
>>
>> ccu_plla_update_param(pll, &pll->config.rate_tbl[0]);
>>
--
Troy Mitchell
Hi Troy,
On 19:20 Sun 06 Sep , Troy Mitchell wrote:
> Hi Yixun, Aurelien
>
> On Sun Sep 6, 2026 at 6:07 AM +08, Yixun Lan wrote:
> > Hi Aurelien, Troy,
> >
> > On 11:24 Fri 04 Sep , Troy Mitchell wrote:
> >> Hi Aurelien,
> >>
> >> On Fri Sep 4, 2026 at 1:27 AM +08, Aurelien Jarno wrote:
> >> > Hi Troy,
> >> >
> > ..
> >> >> drivers/clk/spacemit/ccu-k3.c | 96 +++++++++++++++++++++++++++++++++++++++++++
> >> >> 1 file changed, 96 insertions(+)
> >> >
> >> > Thanks for the patch, it makes sense to add all the values, to support
> >> > future firmware changes. The values match the ones in the vendor kernel.
> >> I forgot that you had a similar patch as well..
> >>
> >> >
> >> >> diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c
> >> >> index 92b930d5ff30..950bf531c734 100644
> >> >> --- a/drivers/clk/spacemit/ccu-k3.c
> >> >> +++ b/drivers/clk/spacemit/ccu-k3.c
> >> >> @@ -29,15 +29,91 @@ static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = {
> >> >> CCU_PLLA_RATE(3000000000UL, 0x0b3e2000, 0x00000000, 0xa0558c8c),
> >> >> };
> >> >>
> >> >> +/* Keep the firmware default as the first entry. */
> >> >> static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = {
> >> >> + CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686),
> >> >
> >> > Is it really necessary to put this entry first? I guess it's the current
> >> > default frequency, but we have seen it can evolve. From my tests, the
> >> > driver seems to just keep the value configured by the firmware
> >> > independently from the table order, so I am not sure it's necessary.
> >
> > I agree with Aurelien here, the default frequency isn't a solid stable settings,
> > which it may changes in the future
> >
> >> I think keeping it first is necessary. If the current register settings do
> >> not match any entry in the table, ccu_plla_init() falls back to the first
> >
> > Isn't it a bug if all frequencies added still couldn't cover all settings?
> > I'd simply suggest to bail out and yell loudly if there is a mismatch
> >
> > I just don't like putting specific frequency at first one as default,
> > this logic is kind of fragile and tend to fail easily..
> I checked the Rockchip PLL driver. The RK3036, RK3066 and RK3399
> implementations calculate the current rate directly from the hardware
> register parameters. If that rate is absent from the rate table, their PLL
> init callbacks return without reprogramming the PLL. With
> ROCKCHIP_PLL_SYNC_RATE enabled, they only synchronize the parameters when
> the current rate matches a table entry but the register parameters differ
> from those in that entry.
>
..
> This approach seems preferable to me. Would it make sense to sort the rate
> tables by frequency in the next revision, and follow up with a separate
> series to calculate the current rate from the registers and preserve
> configurations whose rates are absent from the table, as Rockchip does?
Yes, I generally agree with this approach, so let's push current patch first
ith sorted frequencies, then improve further later in another series.. thanks
--
Yixun Lan (dlan)
Hi Troy,
On 2026-09-04 11:24, Troy Mitchell wrote:
> Hi Aurelien,
>
> On Fri Sep 4, 2026 at 1:27 AM +08, Aurelien Jarno wrote:
> > Hi Troy,
> >
> > On 2026-09-03 11:06, Troy Mitchell wrote:
> >> The K3 CPU PLL rate tables currently describe only one rate per PLL,
> >> although the hardware supports a wider range.
> >>
> >> PLL3 and PLL4 support rates from 1.05 to 2.4 GHz, while PLL5 and PLL8
> >> support rates from 1.05 to 2 GHz. Populate the tables with every
> >> supported rate in 50 MHz steps.
> >>
> >> Cc: stable@vger.kernel.org # 7.0+
> >> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
> >> ---
> >> The corresponding U-Boot changes are available at:
> >>
> >> - Add the CPU PLL rate tables:
> >> https://github.com/spacemit-com/uboot-2022.10/commit/787b5cf44c8dbc99db886d5522c0c9cd5a96ffd6
> >> - Correct the 1.10 GHz and 2.15 GHz table entries:
> >> https://github.com/spacemit-com/uboot-2022.10/commit/16a775c20e9efb54ca55352215e76eb3f12e6cf0
> >> ---
> >> Changes in v4:
> >> - Expand the update to every supported PLL3, PLL4, PLL5 and PLL8 rate.
> >> - Drop Aurelien Jarno's Reviewed-by and Tested-by trailers because the
> >> patch scope has expanded.
> >> - Add U-Boot references for the complete tables and corrected entries.
> >> - Link to v3: https://patch.msgid.link/20260831-k3-pll5-pll8-1800mhz-v3-1-530ed0978615@linux.spacemit.com
> >>
> >> Changes in v3:
> >> - Mark the change for stable kernels starting with v7.0.
> >> - Add Aurelien Jarno's Reviewed-by and Tested-by trailers.
> >> - Rebase onto v7.3-rc1.
> >> - Link to v2: https://patch.msgid.link/20260810-k3-pll5-pll8-1800mhz-v2-1-aabff510a797@linux.spacemit.com
> >>
> >> Changes in v2:
> >> - Drop "clk: spacemit: re-enable PLLs after init"; the PLL init issue
> >> will be handled in a separate series.
> >> - Send the K3 PLL5 and PLL8 1.8 GHz rate-table update as a standalone
> >> patch.
> >> - Clarify that 1.8 GHz is nominal and 2 GHz is an overclocking rate.
> >> - Link to v1: https://patch.msgid.link/20260804-k3-pll5-pll8-1800mhz-v1-0-a3a75866ce32@linux.spacemit.com
> >>
> >> To: Stephen Boyd <sboyd@kernel.org>
> >> To: Brian Masney <bmasney+clk@redhat.com>
> >> To: Jerome Brunet <jbrunet+clk@baylibre.com>
> >> To: Yixun Lan <dlan@kernel.org>
> >> To: Paul Walmsley <pjw@kernel.org>
> >> To: Palmer Dabbelt <palmer@dabbelt.com>
> >> To: Albert Ou <aou@eecs.berkeley.edu>
> >> To: Alexandre Ghiti <alex@ghiti.fr>
> >> Cc: linux-clk@vger.kernel.org
> >> Cc: linux-riscv@lists.infradead.org
> >> Cc: spacemit@lists.linux.dev
> >> Cc: linux-kernel@vger.kernel.org
> >> ---
> >> drivers/clk/spacemit/ccu-k3.c | 96 +++++++++++++++++++++++++++++++++++++++++++
> >> 1 file changed, 96 insertions(+)
> >
> > Thanks for the patch, it makes sense to add all the values, to support
> > future firmware changes. The values match the ones in the vendor kernel.
> I forgot that you had a similar patch as well..
>
> >
> >> diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c
> >> index 92b930d5ff30..950bf531c734 100644
> >> --- a/drivers/clk/spacemit/ccu-k3.c
> >> +++ b/drivers/clk/spacemit/ccu-k3.c
> >> @@ -29,15 +29,91 @@ static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = {
> >> CCU_PLLA_RATE(3000000000UL, 0x0b3e2000, 0x00000000, 0xa0558c8c),
> >> };
> >>
> >> +/* Keep the firmware default as the first entry. */
> >> static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = {
> >> + CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686),
> >
> > Is it really necessary to put this entry first? I guess it's the current
> > default frequency, but we have seen it can evolve. From my tests, the
> > driver seems to just keep the value configured by the firmware
> > independently from the table order, so I am not sure it's necessary.
> I think keeping it first is necessary. If the current register settings do
> not match any entry in the table, ccu_plla_init() falls back to the first
> entry:
>
>
> ccu_plla_update_param(pll, &pll->config.rate_tbl[0]);
>
> [...]
For the A100 cores, that indeed makes sense. For the X100 cores this
line is never reached, as the line above just stops the PLL, basically
stopping the cores:
if (ccu_plla_lookup_matched_entry(pll))
return 0;
ccu_plla_disable(hw);
ccu_plla_update_param(pll, &pll->config.rate_tbl[0]);
Regards
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://aurel32.net
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