This series adds support for the Cadence SD6HC (sixth-generation) SDHCI
controller and enables it on Altera Agilex5 SoCs.

The SD6HC PHY architecture differs substantially from the SD4HC: it
requires dedicated per-speed-mode IO cell timing parameters and a
DLL-based delay line to achieve correct signal margins across all speed
grades from Default Speed through HS400. These are programmed through a
new sdhci-cadence-phy-v6.c file; shared driver infrastructure lives in
sdhci-cadence-core.c.

Note: this series depends on commit ab45ecfab540 ("dt-bindings: reset:
altr: add COMBOPHY_RESET for Agilex5"), which is already in mainline via
the reset tree. It is not yet in mmc/next; apply or merge that commit
when building/testing this series on top of mmc/next. The previous v1/v2
reset binding patch is therefore omitted from this series.

Board DTS files do not enable the SMMU; that is provided by commit
10cf797f3f8a ("arm64: dts: socfpga: agilex5: Enable the SMMU") in the
SoC DT tree. It is not yet in mmc/next. Apply or merge that commit when
building/testing this series on top of mmc/next, otherwise the SMMU
stays disabled in socfpga_agilex5.dtsi.

Patch 1: DT binding
  Adds a dedicated cdns,sd6hc.yaml binding with SD6HC compatible strings,
  clock/reset/IOMMU constraints, and PHY timing properties.

Patches 2-5: Device tree
  Patch 2 adds the SD6HC controller node to the Agilex5 SoC DTSI as
  sdmmc, left disabled.
  Patch 3 enables SD card operation (4-bit, SDR104, 200 MHz) on the
  SOCDK OOBE board with GPIO-switched IO-voltage regulation.
  Patch 4 registers the intel,socfpga-agilex5-socdk-emmc board variant
  in the arm/altera binding.
  Patch 5 adds socfpga_agilex5_socdk_emmc.dts for eMMC-only operation
  (8-bit, HS200/HS400, 1.8 V IO, 200 MHz).

Patches 6-9: Driver
  Patch 6 renames SD4HC-specific functions and structures with a "cdns4"
  prefix to separate them from shared driver paths.
  Patch 7 encapsulates SD4HC PHY probing in sdhci_cdns4_phy_probe() and
  makes every of_device_id entry carry explicit platform data, removing
  the silent fallback.
  Patch 8 introduces the SD6HC PHY driver (sdhci-cadence-phy-v6.c): DLL
  lock/bypass, per-speed-mode IO cell timing, tuning, and HW reset. The
  common driver core selects between v4 and v6 PHY operations based on
  the SDHCI specification version reported by the controller, and
  reprograms the PHY from set_clock and set_uhs_signaling. SD6HC clocks
  are requested by name ("ciu" and "biu").
  Patch 9 adds the Agilex5 platform overlay under altr,agilex5-sd6hc:
  40-bit DMA mask for the SMMU address space, quirks for
  CAP_CLOCK_BASE_BROKEN, PRESET_VALUE_BROKEN, ACMD23_BROKEN and
  MULTIBLOCK_READ_ACMD12, .get_max_clock set to
  sdhci_pltfm_clk_get_max_clock, and an init hook that asserts and
  deasserts the three named resets together, keeping exclusive ownership
  via devm so they stay deasserted for the life of the device.

Tested on Agilex5 SOCDK:
  - SD card: Default Speed, High Speed, SDR25, SDR50, SDR104
  - eMMC daughter board: HS200, HS400

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>

---
Changes in v7:

  [dts]
  - Drop the daughter-card comment from the SoC DTSI (Michael)
    (patch 2).
  - Rename the controller label from emmc to sdmmc to match the HPS
    register map (Michael) (patches 2/3/5).
  - Split SoC node addition from SOCDK SD enablement (Michael)
    (patches 2/3).
  - Drop the DTS comment about SDHCI platform clock order (Michael)
    (patch 2).

  [drivers]
  - Request the SD6HC CIU clock by name ("ciu") instead of relying on
    clocks index 0 (Michael) (patch 8).

Link V6: https://lore.kernel.org/all/20260829184008.10006-1-tanmay.kathpalia@altera.com/
Link V5: https://lore.kernel.org/all/20260820185021.18199-1-tanmay.kathpalia@altera.com/
Link V4: https://lore.kernel.org/all/20260810190025.25045-1-tanmay.kathpalia@altera.com/
Link V3: https://lore.kernel.org/linux-mmc/20260724145009.7456-1-tanmay.kathpalia@altera.com/
Link V2: https://lore.kernel.org/linux-mmc/20260627201457.12318-1-tanmay.kathpalia@altera.com/
Link V1: https://lore.kernel.org/linux-mmc/20260511202132.5597-1-tanmay.kathpalia@altera.com/

Changes in v6:

  [drivers]
  - Use devm_reset_control_bulk_get_exclusive() and keep the exclusive
    reset controls for the lifetime of the device instead of putting
    them after deassert (Philipp) (patch 8).

Changes in v5:

  [bindings]
  - Document driver defaults for cdns,iocell-input-delay-ps (2500),
    cdns,iocell-output-delay-ps (2500), and cdns,delay-element-ps (24)
    (Krzysztof) (patch 1).
  - Collect Reviewed-by from Krzysztof Kozlowski (patch 1).

  [dts]
  - Drop redundant &smmu enablement from the SOCDK and eMMC board DTS
    files. SMMU is enabled by 10cf797f3f8a ("arm64: dts: socfpga:
    agilex5: Enable the SMMU") (Dinh) (patches 2/4).

Changes in v4:

  [bindings]
  - Require the three named resets (sdhc-reset, combophy, sdmmc-ocp) for
    SD6HC nodes. Agilex5 is the first platform using this binding, so the
    Agilex5-only if/then is dropped; a later SoC with different reset
    requirements can reintroduce a compatible-based constraint (patch 1).

  [dts]
  - Note in the commit message that DMA for this controller needs the
    SMMU (stream ID 5) (patch 2).

  [drivers]
  - Add sdhci_cdns6_set_clock() so PHY timings are programmed on clock
    changes (including initial 400 kHz discovery), preferring
    mmc->actual_clock over ios.clock; share the path with
    set_uhs_signaling via sdhci_cdns6_phy_reconfigure() (patches 7/8).
  - Skip redundant PHY reprogramming when mode, rate, and enhanced
    strobe are unchanged; invalidate cached t_sdclk on failure or
    clock-disable (patch 7).
  - Use ios->timing in hs400_enhanced_strobe instead of hardcoding
    MMC_TIMING_MMC_HS400 (patch 7).
  - Program tuning delays with a DLL reset cycle instead of calling
    full phy_init() (patch 7).
  - Cap dll_max_value at 255 in DLL bypass mode so the delay cannot
    wrap when stored in an 8-bit field (patch 7).
  - Reject cdns,delay-element-ps = 0 and fall back to the default with
    a warning (patch 7).
  - Pulse Agilex5 resets with reset_control_bulk_* instead of three
    separate reset_control handles (patch 8).
  - Collect Acked-by tags from Adrian Hunter (patches 5-8) and Conor
    Dooley (patch 3).

Tanmay Kathpalia (9):
  dt-bindings: mmc: add Cadence SD6HC binding
  arm64: dts: agilex5: add SD/eMMC host controller
  arm64: dts: agilex5: enable SD card on SOCDK OOBE card
  dt-bindings: arm: altera: add Agilex5 SOCDK eMMC board variant
  arm64: dts: agilex5: add SOCDK eMMC daughter board
  mmc: sdhci-cadence: rename SD4HC symbols for SD6HC groundwork
  mmc: sdhci-cadence: refactor driver structure for V6 controller
    support
  mmc: sdhci-cadence: add Cadence SD6HC support
  mmc: sdhci-cadence: add Altera Agilex5 SD6HC support

 .../devicetree/bindings/arm/altera.yaml       |   1 +
 .../devicetree/bindings/mmc/cdns,sd6hc.yaml   | 105 ++
 MAINTAINERS                                   |   7 +
 arch/arm64/boot/dts/intel/Makefile            |   1 +
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi |  15 +
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  34 +-
 .../dts/intel/socfpga_agilex5_socdk_emmc.dts  | 123 +++
 drivers/mmc/host/Makefile                     |   1 +
 .../{sdhci-cadence.c => sdhci-cadence-core.c} | 303 ++++--
 drivers/mmc/host/sdhci-cadence-phy-v6.c       | 975 ++++++++++++++++++
 drivers/mmc/host/sdhci-cadence.h              | 118 +++
 11 files changed, 1608 insertions(+), 75 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mmc/cdns,sd6hc.yaml
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_emmc.dts
 rename drivers/mmc/host/{sdhci-cadence.c => sdhci-cadence-core.c} (67%)
 create mode 100644 drivers/mmc/host/sdhci-cadence-phy-v6.c
 create mode 100644 drivers/mmc/host/sdhci-cadence.h

-- 
2.43.7

Hi Ulf, Dinh,

A gentle ping on this series.

All comments from the earlier revisions have been addressed. Patch 1
carries a Reviewed-by from Krzysztof Kozlowski, patch 4 an Acked-by
from Conor Dooley, and patches 6-9 an Acked-by from Adrian Hunter.
Thanks to everyone who reviewed it.

Could you please pick up the patches that belong in your trees?

Both dependencies noted in the cover letter are now in mainline:
ab45ecfab540 ("dt-bindings: reset: altr: add COMBOPHY_RESET for
Agilex5") since v7.2-rc4, and 10cf797f3f8a ("arm64: dts: socfpga:
agilex5: Enable the SMMU") since v7.3-rc1. The patches were generated on
mmc/next, which predates both, so those commits need to be merged first
if the DT patches are applied there.

Thanks,
Tanmay

On 9/2/2026 12:18 AM, Tanmay Kathpalia wrote:
> This series adds support for the Cadence SD6HC (sixth-generation) SDHCI
> controller and enables it on Altera Agilex5 SoCs.
>

On 9/11/26 02:35, Kathpalia, Tanmay wrote:
> Hi Ulf, Dinh,
> 
> A gentle ping on this series.
> 
> All comments from the earlier revisions have been addressed. Patch 1
> carries a Reviewed-by from Krzysztof Kozlowski, patch 4 an Acked-by
> from Conor Dooley, and patches 6-9 an Acked-by from Adrian Hunter.
> Thanks to everyone who reviewed it.
> 
> Could you please pick up the patches that belong in your trees?
> 
> Both dependencies noted in the cover letter are now in mainline:
> ab45ecfab540 ("dt-bindings: reset: altr: add COMBOPHY_RESET for
> Agilex5") since v7.2-rc4, and 10cf797f3f8a ("arm64: dts: socfpga:
> agilex5: Enable the SMMU") since v7.3-rc1. The patches were generated on
> mmc/next, which predates both, so those commits need to be merged first
> if the DT patches are applied there.
> 
I've queue the following patches locally, but waiting on the SDHC 
maintainers to take the driver portion.

[2/9] arm64: dts: agilex5: add SD/eMMC host controller
       commit: c2b598317688f8e599bf6ca048863db311482450
[3/9] arm64: dts: agilex5: enable SD card on SOCDK OOBE card
       commit: 65a8ab194ffb427bd2ae37a1da54710eddf10845
[4/9] dt-bindings: arm: altera: add Agilex5 SOCDK eMMC board variant
       commit: f78580fddb9b9d39eaea23f847a53b0ce974687b

Dinh

On Tue, Sep 1, 2026 at 8:49 PM Tanmay Kathpalia
<tanmay.kathpalia@altera.com> wrote:
>
> This series adds support for the Cadence SD6HC (sixth-generation) SDHCI
> controller and enables it on Altera Agilex5 SoCs.
>
> The SD6HC PHY architecture differs substantially from the SD4HC: it
> requires dedicated per-speed-mode IO cell timing parameters and a
> DLL-based delay line to achieve correct signal margins across all speed
> grades from Default Speed through HS400. These are programmed through a
> new sdhci-cadence-phy-v6.c file; shared driver infrastructure lives in
> sdhci-cadence-core.c.
>
> Note: this series depends on commit ab45ecfab540 ("dt-bindings: reset:
> altr: add COMBOPHY_RESET for Agilex5"), which is already in mainline via
> the reset tree. It is not yet in mmc/next; apply or merge that commit
> when building/testing this series on top of mmc/next. The previous v1/v2
> reset binding patch is therefore omitted from this series.
>
> Board DTS files do not enable the SMMU; that is provided by commit
> 10cf797f3f8a ("arm64: dts: socfpga: agilex5: Enable the SMMU") in the
> SoC DT tree. It is not yet in mmc/next. Apply or merge that commit when
> building/testing this series on top of mmc/next, otherwise the SMMU
> stays disabled in socfpga_agilex5.dtsi.
>
> Patch 1: DT binding
>   Adds a dedicated cdns,sd6hc.yaml binding with SD6HC compatible strings,
>   clock/reset/IOMMU constraints, and PHY timing properties.
>
> Patches 2-5: Device tree
>   Patch 2 adds the SD6HC controller node to the Agilex5 SoC DTSI as
>   sdmmc, left disabled.
>   Patch 3 enables SD card operation (4-bit, SDR104, 200 MHz) on the
>   SOCDK OOBE board with GPIO-switched IO-voltage regulation.
>   Patch 4 registers the intel,socfpga-agilex5-socdk-emmc board variant
>   in the arm/altera binding.
>   Patch 5 adds socfpga_agilex5_socdk_emmc.dts for eMMC-only operation
>   (8-bit, HS200/HS400, 1.8 V IO, 200 MHz).
>
> Patches 6-9: Driver
>   Patch 6 renames SD4HC-specific functions and structures with a "cdns4"
>   prefix to separate them from shared driver paths.
>   Patch 7 encapsulates SD4HC PHY probing in sdhci_cdns4_phy_probe() and
>   makes every of_device_id entry carry explicit platform data, removing
>   the silent fallback.
>   Patch 8 introduces the SD6HC PHY driver (sdhci-cadence-phy-v6.c): DLL
>   lock/bypass, per-speed-mode IO cell timing, tuning, and HW reset. The
>   common driver core selects between v4 and v6 PHY operations based on
>   the SDHCI specification version reported by the controller, and
>   reprograms the PHY from set_clock and set_uhs_signaling. SD6HC clocks
>   are requested by name ("ciu" and "biu").
>   Patch 9 adds the Agilex5 platform overlay under altr,agilex5-sd6hc:
>   40-bit DMA mask for the SMMU address space, quirks for
>   CAP_CLOCK_BASE_BROKEN, PRESET_VALUE_BROKEN, ACMD23_BROKEN and
>   MULTIBLOCK_READ_ACMD12, .get_max_clock set to
>   sdhci_pltfm_clk_get_max_clock, and an init hook that asserts and
>   deasserts the three named resets together, keeping exclusive ownership
>   via devm so they stay deasserted for the life of the device.
>
> Tested on Agilex5 SOCDK:
>   - SD card: Default Speed, High Speed, SDR25, SDR50, SDR104
>   - eMMC daughter board: HS200, HS400
>
> Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
>
> ---
> Changes in v7:
>

[...]

Patch 1 and 6-9 from the v7 series, applied for next, thanks!

Kind regards
Uffe

On 9/11/26 10:40, Ulf Hansson wrote:
> On Tue, Sep 1, 2026 at 8:49 PM Tanmay Kathpalia
> <tanmay.kathpalia@altera.com> wrote:
>>
>> This series adds support for the Cadence SD6HC (sixth-generation) SDHCI
>> controller and enables it on Altera Agilex5 SoCs.
>>
>> The SD6HC PHY architecture differs substantially from the SD4HC: it
>> requires dedicated per-speed-mode IO cell timing parameters and a
>> DLL-based delay line to achieve correct signal margins across all speed
>> grades from Default Speed through HS400. These are programmed through a
>> new sdhci-cadence-phy-v6.c file; shared driver infrastructure lives in
>> sdhci-cadence-core.c.
>>
>> Note: this series depends on commit ab45ecfab540 ("dt-bindings: reset:
>> altr: add COMBOPHY_RESET for Agilex5"), which is already in mainline via
>> the reset tree. It is not yet in mmc/next; apply or merge that commit
>> when building/testing this series on top of mmc/next. The previous v1/v2
>> reset binding patch is therefore omitted from this series.
>>
>> Board DTS files do not enable the SMMU; that is provided by commit
>> 10cf797f3f8a ("arm64: dts: socfpga: agilex5: Enable the SMMU") in the
>> SoC DT tree. It is not yet in mmc/next. Apply or merge that commit when
>> building/testing this series on top of mmc/next, otherwise the SMMU
>> stays disabled in socfpga_agilex5.dtsi.
>>
>> Patch 1: DT binding
>>    Adds a dedicated cdns,sd6hc.yaml binding with SD6HC compatible strings,
>>    clock/reset/IOMMU constraints, and PHY timing properties.
>>
>> Patches 2-5: Device tree
>>    Patch 2 adds the SD6HC controller node to the Agilex5 SoC DTSI as
>>    sdmmc, left disabled.
>>    Patch 3 enables SD card operation (4-bit, SDR104, 200 MHz) on the
>>    SOCDK OOBE board with GPIO-switched IO-voltage regulation.
>>    Patch 4 registers the intel,socfpga-agilex5-socdk-emmc board variant
>>    in the arm/altera binding.
>>    Patch 5 adds socfpga_agilex5_socdk_emmc.dts for eMMC-only operation
>>    (8-bit, HS200/HS400, 1.8 V IO, 200 MHz).
>>
>> Patches 6-9: Driver
>>    Patch 6 renames SD4HC-specific functions and structures with a "cdns4"
>>    prefix to separate them from shared driver paths.
>>    Patch 7 encapsulates SD4HC PHY probing in sdhci_cdns4_phy_probe() and
>>    makes every of_device_id entry carry explicit platform data, removing
>>    the silent fallback.
>>    Patch 8 introduces the SD6HC PHY driver (sdhci-cadence-phy-v6.c): DLL
>>    lock/bypass, per-speed-mode IO cell timing, tuning, and HW reset. The
>>    common driver core selects between v4 and v6 PHY operations based on
>>    the SDHCI specification version reported by the controller, and
>>    reprograms the PHY from set_clock and set_uhs_signaling. SD6HC clocks
>>    are requested by name ("ciu" and "biu").
>>    Patch 9 adds the Agilex5 platform overlay under altr,agilex5-sd6hc:
>>    40-bit DMA mask for the SMMU address space, quirks for
>>    CAP_CLOCK_BASE_BROKEN, PRESET_VALUE_BROKEN, ACMD23_BROKEN and
>>    MULTIBLOCK_READ_ACMD12, .get_max_clock set to
>>    sdhci_pltfm_clk_get_max_clock, and an init hook that asserts and
>>    deasserts the three named resets together, keeping exclusive ownership
>>    via devm so they stay deasserted for the life of the device.
>>
>> Tested on Agilex5 SOCDK:
>>    - SD card: Default Speed, High Speed, SDR25, SDR50, SDR104
>>    - eMMC daughter board: HS200, HS400
>>
>> Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
>>
>> ---
>> Changes in v7:
>>
> 
> [...]
> 
> Patch 1 and 6-9 from the v7 series, applied for next, thanks!
> 
Patch 2,3,4,5 appled for next.

Thanks,
Dinh