.../devicetree/bindings/pci/qcom,shikra-pcie.yaml | 218 +++++++++++++++++++++ .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 + arch/arm64/boot/dts/qcom/shikra.dtsi | 159 ++++++++++++++- drivers/pci/controller/dwc/pcie-qcom.c | 1 + drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 73 +++++++ 5 files changed, 452 insertions(+), 1 deletion(-)
Add PCIe support for Shikra target, by adding dt-bindings for phy,
controller and corresponding phy & controller drivers/device-tree
changes.
Shikra RC is connected to TC9563 PCIe switch on all three
EVK variants: CQS, CQM and IQS. The individual downstream ports
of TC9563 connect like below:
DSP1: M.2 B-Key for 5G Modem
DSP2: M.2 M-Key for NVMe
DSP3: Embedded ethernet device
Power and reset to M.2 B and M.2 M slot are controlled via
TC9563 GPIO's. Since TC9563 GPIO driver from Alex is still
under active review, current series only contains basic PCIe
enablement for the controller / PHY. TC9563 enablement changes
would be posted as a separate series once the GPIO driver is
ready.
[1] https://lore.kernel.org/all/e2inl7k5gsjj6oomv2k5ximuzpb3gfiz66ufet3b4hvov7zqt4@qz4pifbos7yf/
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
Changes in v2:
- Remove TC9563 specific changes [Mani]
- Fix commit descriptions/subjects [Bjorn Helgaas]
- Fix PCIe controller dt-binding errors [Krzysztof Kozlowski / Mani]
- Document PCIe Gen2 limitation in controller node & commit msg [Konrad Dybcio / Mani]
- Add GCC_PCIE_SLEEP_CLK (which is actually PHY AUX CLK) in PCIe PHY
node.
- Link to v1: https://lore.kernel.org/r/20260701-shikra-upstream-v1-0-e1a721eb8943@oss.qualcomm.com
---
Sushrut Shree Trivedi (5):
dt-bindings: phy: sc8280xp-qmp-pcie: Document Shikra PCIe phy
dt-bindings: PCI: qcom,shikra-pcie: Document the Shikra PCIe Controller
PCI: qcom: Add support for Shikra
phy: qcom: qmp-pcie: Add QMP PCIe PHY support for Shikra
arm64: dts: qcom: shikra: Add PCIe PHY and controller nodes
.../devicetree/bindings/pci/qcom,shikra-pcie.yaml | 218 +++++++++++++++++++++
.../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 +
arch/arm64/boot/dts/qcom/shikra.dtsi | 159 ++++++++++++++-
drivers/pci/controller/dwc/pcie-qcom.c | 1 +
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 73 +++++++
5 files changed, 452 insertions(+), 1 deletion(-)
---
base-commit: 565fa02f75448ce1ddd18bda6b31ad985cf75411
change-id: 20260701-shikra-upstream-14b8668f1001
Best regards,
--
Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
On 8/31/26 9:26 AM, Sushrut Shree Trivedi wrote: > Add PCIe support for Shikra target, by adding dt-bindings for phy, > controller and corresponding phy & controller drivers/device-tree > changes. > > Shikra RC is connected to TC9563 PCIe switch on all three > EVK variants: CQS, CQM and IQS. The individual downstream ports > of TC9563 connect like below: > > DSP1: M.2 B-Key for 5G Modem > DSP2: M.2 M-Key for NVMe > DSP3: Embedded ethernet device > > Power and reset to M.2 B and M.2 M slot are controlled via > TC9563 GPIO's. Since TC9563 GPIO driver from Alex is still > under active review, current series only contains basic PCIe > enablement for the controller / PHY. TC9563 enablement changes > would be posted as a separate series once the GPIO driver is > ready. > > [1] https://lore.kernel.org/all/e2inl7k5gsjj6oomv2k5ximuzpb3gfiz66ufet3b4hvov7zqt4@qz4pifbos7yf/ > > Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com> > --- > Changes in v2: > - Remove TC9563 specific changes [Mani] > - Fix commit descriptions/subjects [Bjorn Helgaas] > - Fix PCIe controller dt-binding errors [Krzysztof Kozlowski / Mani] > - Document PCIe Gen2 limitation in controller node & commit msg [Konrad Dybcio / Mani] > - Add GCC_PCIE_SLEEP_CLK (which is actually PHY AUX CLK) in PCIe PHY > node. You also silently adjusted the OPP levels in the DT patch: < + required-opps = <&rpmpd_opp_nom>; --- > + required-opps = <&rpmpd_opp_low_svs>; is the lower one suitable? Konrad
On 9/2/2026 2:16 PM, Konrad Dybcio wrote: > On 8/31/26 9:26 AM, Sushrut Shree Trivedi wrote: >> Add PCIe support for Shikra target, by adding dt-bindings for phy, >> controller and corresponding phy & controller drivers/device-tree >> changes. >> >> Shikra RC is connected to TC9563 PCIe switch on all three >> EVK variants: CQS, CQM and IQS. The individual downstream ports >> of TC9563 connect like below: >> >> DSP1: M.2 B-Key for 5G Modem >> DSP2: M.2 M-Key for NVMe >> DSP3: Embedded ethernet device >> >> Power and reset to M.2 B and M.2 M slot are controlled via >> TC9563 GPIO's. Since TC9563 GPIO driver from Alex is still >> under active review, current series only contains basic PCIe >> enablement for the controller / PHY. TC9563 enablement changes >> would be posted as a separate series once the GPIO driver is >> ready. >> >> [1] https://lore.kernel.org/all/e2inl7k5gsjj6oomv2k5ximuzpb3gfiz66ufet3b4hvov7zqt4@qz4pifbos7yf/ >> >> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com> >> --- >> Changes in v2: >> - Remove TC9563 specific changes [Mani] >> - Fix commit descriptions/subjects [Bjorn Helgaas] >> - Fix PCIe controller dt-binding errors [Krzysztof Kozlowski / Mani] >> - Document PCIe Gen2 limitation in controller node & commit msg [Konrad Dybcio / Mani] >> - Add GCC_PCIE_SLEEP_CLK (which is actually PHY AUX CLK) in PCIe PHY >> node. > You also silently adjusted the OPP levels in the DT patch: My bad; I did ACK Mani's comment in v1 regarding higher voltage corner votes. Will mention in cover letter next time onwards. > > < + required-opps = <&rpmpd_opp_nom>; > --- >> + required-opps = <&rpmpd_opp_low_svs>; > > is the lower one suitable? Yes, Gen2 can be supported with low svs corner as per HW team. > > Konrad
On Mon, 31 Aug 2026 12:56:00 +0530, Sushrut Shree Trivedi wrote:
> Add PCIe support for Shikra target, by adding dt-bindings for phy,
> controller and corresponding phy & controller drivers/device-tree
> changes.
>
> Shikra RC is connected to TC9563 PCIe switch on all three
> EVK variants: CQS, CQM and IQS. The individual downstream ports
> of TC9563 connect like below:
>
> [...]
Applied, thanks!
[1/5] dt-bindings: phy: sc8280xp-qmp-pcie: Document Shikra PCIe phy
commit: 0f654af456b5e347dd69d58c2fc6d7e17c36a6d1
[4/5] phy: qcom: qmp-pcie: Add QMP PCIe PHY support for Shikra
commit: 3518d967d8b64485f9dbf90bfeba1f341ef4c131
Best regards,
--
~Vinod
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