Section 4.2 of YACG4D0C9SHC(Hi-846) datasheet specifies the time
between XSHUTDOWN rising and RESETB rising (t3-1) and RESETB rising
to the first I2C transaction (t3-2) to be both at least 2400 MCLK
cycles. This driver currently requires the MCLK rate to be set to
25 MHz, so t3-1 and t3-2 need to be at least 96 µs.

On top of that, Figure 14 shows that RESETB needs to be held for
at least 120 MCLK cycles. Ensure that this is the case.

Fixes: e8c0882685f9 ("media: i2c: add driver for the SK Hynix Hi-846 8M pixel camera")
Cc: stable@vger.kernel.org
Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm>
---
 drivers/media/i2c/hi846.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/media/i2c/hi846.c b/drivers/media/i2c/hi846.c
index a3f77b8434ca..d58940c8da20 100644
--- a/drivers/media/i2c/hi846.c
+++ b/drivers/media/i2c/hi846.c
@@ -1643,11 +1643,16 @@ static int hi846_power_on(struct hi846 *hi846)
 	if (hi846->shutdown_gpio)
 		gpiod_set_value_cansleep(hi846->shutdown_gpio, 0);
 
-	/* 30us = 2400 cycles at 80Mhz */
-	usleep_range(30, 60);
-	if (hi846->rst_gpio)
+	/* 96us = 2400 cycles at 25MHz */
+	usleep_range(96, 120);
+
+	if (hi846->rst_gpio) {
+		gpiod_set_value_cansleep(hi846->rst_gpio, 1);
+		/* 5us = 120 cycles at 25MHz */
+		usleep_range(5, 10);
 		gpiod_set_value_cansleep(hi846->rst_gpio, 0);
-	usleep_range(30, 60);
+		usleep_range(96, 120);
+	}
 
 	return 0;
 

---
base-commit: e30626823a406725ce29bc75cb8ec467d3e1e326
change-id: 20260831-hi846-poweronseq-71e7ac35401b

Best regards,
--  
Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm>

Hi Sebastian,

Thanks for the patch.

On Mon, Aug 31, 2026 at 12:13:32AM +0200, Sebastian Krzyszkowiak wrote:
> Section 4.2 of YACG4D0C9SHC(Hi-846) datasheet specifies the time
> between XSHUTDOWN rising and RESETB rising (t3-1) and RESETB rising
> to the first I2C transaction (t3-2) to be both at least 2400 MCLK
> cycles. This driver currently requires the MCLK rate to be set to
> 25 MHz, so t3-1 and t3-2 need to be at least 96 µs.

Could you calculate the required delay instead of usign static value? The
minimum external clock frequency for the sensor appears to be 10 MHz.

-- 
Regards,

Sakari Ailus