arch/arm64/boot/dts/qcom/shikra.dtsi | 52 ++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+)
Add device tree nodes describing the crypto hardware blocks present
on the Qualcomm Shikra platform:
- BAM DMA controller used by the Qualcomm crypto engine
- QCE (crypto) engine with DMA support
- TRNG hardware random number generator
- Inline crypto engine (ICE)
Also connect the SDHC controller to ICE via "qcom,ice" property to
support inline encryption.
On Shikra, different BAM pipe pairs (for example 0x84/0x94 and
0x86/0x96) may still resolve to the same resulting SID due SMMU-side
optimization. They are still distinct pipe pairs and therefore require
separate DT IOMMU entries.
Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
This patch series enables SDHC ICE, RNG and QCE support on Shikra,
aligned with how similar support is modeled on other Qualcomm platforms.
Keeping just dts patch as rest all patches got merged.
---
Changes in v5:
- Rebase onto latest linux-next; patches 1-5 of v4 are merged.
- Update sdhc_ice power domain to match sdhc_1 PD.(Sashiko review).
- Link to v4: https://patch.msgid.link/20260714-b4-shikra_crypto_changse-v4-0-06a4ea97c209@oss.qualcomm.com
Changes in v4:
- Update Patch 1/6 commit message to accustom hawi special case.
- Collects tags(Krzysztof)
- Link to v3: https://patch.msgid.link/20260706-b4-shikra_crypto_changse-v3-0-23b4c2054227@oss.qualcomm.com
Changes in v3:
- Fix commit messages.
- Collect Ack and Reviewed-by tags.
- Link to v2: https://patch.msgid.link/20260702-b4-shikra_crypto_changse-v2-0-66173f2f28b3@qti.qualcomm.com
Changes in v2:
- Add fix in ice bindings to specify 2 clocks defauly for non-legacy Soc
compatibles.
- Update commit messages.
- Link to v1: https://patch.msgid.link/20260521-shikra_crypto_changse-v1-0-0154cc9cc0de@oss.qualcomm.com/
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 52 ++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 92d22e3b6931..4815effba4ef 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -962,6 +962,41 @@ config_noc: interconnect@1900000 {
#interconnect-cells = <2>;
};
+ cryptobam: dma-controller@1b04000 {
+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+ reg = <0x0 0x01b04000 0x0 0x24000>;
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>;
+ #dma-cells = <1>;
+ iommus = <&apps_smmu 0x84 0x0011>,
+ <&apps_smmu 0x86 0x0011>,
+ <&apps_smmu 0x92 0x0>,
+ <&apps_smmu 0x94 0x0011>,
+ <&apps_smmu 0x96 0x0011>,
+ <&apps_smmu 0x98 0x0001>,
+ <&apps_smmu 0x9f 0x0>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ num-channels = <16>;
+ qcom,num-ees = <4>;
+ };
+
+ crypto: crypto@1b3a000 {
+ compatible = "qcom,shikra-qce", "qcom,sm8150-qce", "qcom,qce";
+ reg = <0x0 0x01b3a000 0x0 0x6000>;
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x84 0x0011>,
+ <&apps_smmu 0x86 0x0011>,
+ <&apps_smmu 0x92 0x0>,
+ <&apps_smmu 0x94 0x0011>,
+ <&apps_smmu 0x96 0x0011>,
+ <&apps_smmu 0x98 0x0001>,
+ <&apps_smmu 0x9f 0x0>;
+ interconnects = <&system_noc MASTER_CRYPTO_CORE0 0
+ &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "memory";
+ };
+
qfprom: efuse@1b44000 {
compatible = "qcom,shikra-qfprom", "qcom,qfprom";
reg = <0x0 0x01b44000 0x0 0x3000>;
@@ -1013,6 +1048,11 @@ tsens0: thermal-sensor@4411000 {
#thermal-sensor-cells = <1>;
};
+ rng: rng@4454000 {
+ compatible = "qcom,shikra-trng", "qcom,trng";
+ reg = <0x0 0x04454000 0x0 0x1000>;
+ };
+
rpm_msg_ram: sram@45f0000 {
compatible = "qcom,rpm-msg-ram", "mmio-sram";
reg = <0x0 0x045f0000 0x0 0x7000>;
@@ -1074,6 +1114,7 @@ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
mmc-hs400-enhanced-strobe;
resets = <&gcc GCC_SDCC1_BCR>;
+ qcom,ice = <&sdhc_ice>;
status = "disabled";
@@ -1096,6 +1137,17 @@ opp-384000000 {
};
};
+ sdhc_ice: crypto@4748000 {
+ compatible = "qcom,shikra-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0x0 0x04748000 0x0 0x18000>;
+ clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>;
+ clock-names = "core",
+ "iface";
+ power-domains = <&rpmpd RPMPD_VDDCX>;
+ };
+
gpi_dma0: dma-controller@4a00000 {
compatible = "qcom,shikra-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x04a00000 0x0 0x60000>;
---
base-commit: e6664f2b33db9b6811eb4cec109f06cb2b4f458d
change-id: 20260701-b4-shikra_crypto_changse-f2d6d5bf04b5
Best regards,
--
Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>On 20-08-2026 16:23, Kuldeep Singh wrote: > Add device tree nodes describing the crypto hardware blocks present > on the Qualcomm Shikra platform: > > - BAM DMA controller used by the Qualcomm crypto engine > - QCE (crypto) engine with DMA support > - TRNG hardware random number generator > - Inline crypto engine (ICE) > > Also connect the SDHC controller to ICE via "qcom,ice" property to > support inline encryption. > > On Shikra, different BAM pipe pairs (for example 0x84/0x94 and > 0x86/0x96) may still resolve to the same resulting SID due SMMU-side > optimization. They are still distinct pipe pairs and therefore require > separate DT IOMMU entries. > > Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com> > Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>-- Hi Bjorn/Herbert, Shikra is actually derivative of agatti which is following a different crypto(qce) configuration different from other targets. https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/crypto/qcom-qce.yaml#n40 The current qce _is_ still working by not voting for the clocks as clk-smd-rpm driver was doing proxy voting. In recent discussion with clocks team, it's identified that clk-smd-rpm driver will drop proxy voting and recommendation for qce is to vote for clocks explicitly. I'll be sending v6 with the change ASAP follwing agatti's convention. https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/qcom/agatti.dtsi#n889 Sorry for inconvenience!! as I see patches are applied in the tree. Regards Kuldeep
On Thu, 20 Aug 2026 16:23:43 +0530, Kuldeep Singh wrote:
> Add device tree nodes describing the crypto hardware blocks present
> on the Qualcomm Shikra platform:
>
> - BAM DMA controller used by the Qualcomm crypto engine
> - QCE (crypto) engine with DMA support
> - TRNG hardware random number generator
> - Inline crypto engine (ICE)
>
> [...]
Applied, thanks!
[1/1] arm64: dts: qcom: shikra: Add ICE, TRNG and QCE nodes
commit: 099cd05d200ba241bcc7497c4384b8d657a5632e
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
On 26-08-20 16:23:43, Kuldeep Singh wrote: > Add device tree nodes describing the crypto hardware blocks present > on the Qualcomm Shikra platform: > > - BAM DMA controller used by the Qualcomm crypto engine > - QCE (crypto) engine with DMA support > - TRNG hardware random number generator > - Inline crypto engine (ICE) > > Also connect the SDHC controller to ICE via "qcom,ice" property to > support inline encryption. > > On Shikra, different BAM pipe pairs (for example 0x84/0x94 and > 0x86/0x96) may still resolve to the same resulting SID due SMMU-side > optimization. They are still distinct pipe pairs and therefore require > separate DT IOMMU entries. > > Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com> > Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
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