From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

Agilex5 GMAC instances expose per-DMA-channel TX/RX completion SPIs.
Common stmmac already parses interrupt-names "tx-queue-N" / "rx-queue-N"
and can request them when STMMAC_FLAG_MULTI_MSI_EN is set.

This series mirrors dwmac-s32: enable that flag from dwmac-socfpga when
all configured queue IRQs are present, and describe those IRQs in the
Agilex5 DTSI with upstream names (no vendor-specific macirq_tx*/rx* or
snps,multi-irq-en binding).

Patch 1 is for netdev; patch 2 for SoCFPGA/arm64 DT.

Nazim Amirul (2):
  net: stmmac: dwmac-socfpga: Enable multi-IRQ when per-queue IRQs
    present
  arm64: dts: intel: agilex5: Add per-queue GMAC interrupts

 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 108 +++++++++++++++++-
 .../ethernet/stmicro/stmmac/dwmac-socfpga.c   |  31 +++++
 2 files changed, 133 insertions(+), 6 deletions(-)

-- 
2.43.7