From: pguo <peng.guo@montage-tech.com>

When MMPT is enabled, a device may expose PCI-SIG-defined MMPT
capabilities alongside CXL-defined capabilities in the same MMIO
Capabilities Register Block (MCAP).

MCAP capability IDs are scoped by Vendor ID, but the CXL capability
parser currently matches entries using only their capability IDs. This
can cause MMPT entries to be interpreted as CXL register blocks.

Add the generic PCI MCAP register definitions, then update the CXL
parser to process only capabilities carrying the CXL Vendor ID.

Patch 1 adds the PCI MCAP array and capability header definitions.
Patch 2 filters non-CXL capabilities before interpreting their IDs.

The fix has been tested on a CXL device with MMPT enabled and prevents
both the Mailbox and Status capability misidentification.

pguo (2):
  PCI: Add MMIO Capabilities Register Block definitions
  cxl/core: Skip non-CXL capabilities in MCAP

 drivers/cxl/core/regs.c       |  8 +++++++-
 include/uapi/linux/pci_regs.h | 21 +++++++++++++++++++++
 2 files changed, 28 insertions(+), 1 deletion(-)

-- 
2.43.0