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[PATCH v2] drm/i915/cdclk: Don't force cd2x pipe select on Xe3 in bxt_sanitize_cdclk()

Chang Jiong(常炯) posted 1 patch 1 month, 1 week ago 
drivers/gpu/drm/i915/display/intel_cdclk.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
[PATCH v2] drm/i915/cdclk: Don't force cd2x pipe select on Xe3 in bxt_sanitize_cdclk()
Posted by Chang Jiong(常炯) 1 month, 1 week ago 
Since commit 2ee8dbd880b1 ("drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL
without a full PLL re-enable") bxt_sanitize_cdclk() normalizes the
CD2X pipe select field of the CDCLK_CTL readback to PIPE_NONE before
comparing against the expected value.

However bxt_cdclk_ctl() does not include the CD2X pipe select field
at all on DISPLAY_VER() >= 30, so on Xe3 (PTL) the normalized
readback (pipe field forced to the PIPE_NONE encoding, 0b111) can
never match the expected value (pipe field 0). The comparison now
fails on every boot and we always take the full CDCLK PLL
disable+re-enable path with the BIOS framebuffer actively scanning
out - exactly what this code was trying to avoid. On a Panther Lake
laptop (Arc B390, 8086:b080, eDP 3120x2080@120) this causes
"CPU pipe A FIFO underrun" during probe and persistent full-screen
scanout corruption for the first KMS client (the SDDM greeter);
the corruption lasts until the next full modeset.

Only normalize the CD2X pipe select field on platforms where
bxt_cdclk_ctl() actually programs it, mirroring its DISPLAY_VER()
check.

Fixes: 2ee8dbd880b1 ("drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL without a full PLL re-enable")
Cc: stable@vger.kernel.org
Signed-off-by: Chang Jiong(常炯) <xspeed1989@gmail.com>
---
v2: No code changes. Resent with From matching Signed-off-by
    (v1 was sent from 304750714@qq.com, which is not on the
    Intel CI allowlist).

 drivers/gpu/drm/i915/display/intel_cdclk.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 7bc9b956554b..0438f5ac78c0 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2366,8 +2366,10 @@ static void bxt_sanitize_cdclk(struct intel_display *display)
 	 * dividers both syncing to an active pipe, or asynchronously
 	 * (PIPE_NONE).
 	 */
-	cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
-	cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
+	if (DISPLAY_VER(display) < 30) {
+		cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
+		cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
+	}
 
 	if (cdctl != expected) {
 		if (DISPLAY_VER(display) < 20) {
-- 
2.55.0
Re: [PATCH v2] drm/i915/cdclk: Don't force cd2x pipe select on Xe3 in bxt_sanitize_cdclk()
Posted by Jani Nikula 1 month, 1 week ago 
On Sun, 16 Aug 2026, Chang Jiong(常炯) <xspeed1989@gmail.com> wrote:
> Since commit 2ee8dbd880b1 ("drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL
> without a full PLL re-enable") bxt_sanitize_cdclk() normalizes the
> CD2X pipe select field of the CDCLK_CTL readback to PIPE_NONE before
> comparing against the expected value.
>
> However bxt_cdclk_ctl() does not include the CD2X pipe select field
> at all on DISPLAY_VER() >= 30, so on Xe3 (PTL) the normalized
> readback (pipe field forced to the PIPE_NONE encoding, 0b111) can
> never match the expected value (pipe field 0). The comparison now
> fails on every boot and we always take the full CDCLK PLL
> disable+re-enable path with the BIOS framebuffer actively scanning
> out - exactly what this code was trying to avoid. On a Panther Lake
> laptop (Arc B390, 8086:b080, eDP 3120x2080@120) this causes
> "CPU pipe A FIFO underrun" during probe and persistent full-screen
> scanout corruption for the first KMS client (the SDDM greeter);
> the corruption lasts until the next full modeset.
>
> Only normalize the CD2X pipe select field on platforms where
> bxt_cdclk_ctl() actually programs it, mirroring its DISPLAY_VER()
> check.
>
> Fixes: 2ee8dbd880b1 ("drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL without a full PLL re-enable")
> Cc: stable@vger.kernel.org
> Signed-off-by: Chang Jiong(常炯) <xspeed1989@gmail.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8550
Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8569
Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8901

The first one has a patch from Ville that is identical to this one.

I'll try to kick CI to get this tested before merging.

> ---
> v2: No code changes. Resent with From matching Signed-off-by
>     (v1 was sent from 304750714@qq.com, which is not on the
>     Intel CI allowlist).
>
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 7bc9b956554b..0438f5ac78c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2366,8 +2366,10 @@ static void bxt_sanitize_cdclk(struct intel_display *display)
>  	 * dividers both syncing to an active pipe, or asynchronously
>  	 * (PIPE_NONE).
>  	 */
> -	cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
> -	cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
> +	if (DISPLAY_VER(display) < 30) {
> +		cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
> +		cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
> +	}
>  
>  	if (cdctl != expected) {
>  		if (DISPLAY_VER(display) < 20) {

-- 
Jani Nikula, Intel
Re: [PATCH v2] drm/i915/cdclk: Don't force cd2x pipe select on Xe3 in bxt_sanitize_cdclk()
Posted by Jani Nikula 1 month, 1 week ago 
On Tue, 18 Aug 2026, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Sun, 16 Aug 2026, Chang Jiong(常炯) <xspeed1989@gmail.com> wrote:
>> Since commit 2ee8dbd880b1 ("drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL
>> without a full PLL re-enable") bxt_sanitize_cdclk() normalizes the
>> CD2X pipe select field of the CDCLK_CTL readback to PIPE_NONE before
>> comparing against the expected value.
>>
>> However bxt_cdclk_ctl() does not include the CD2X pipe select field
>> at all on DISPLAY_VER() >= 30, so on Xe3 (PTL) the normalized
>> readback (pipe field forced to the PIPE_NONE encoding, 0b111) can
>> never match the expected value (pipe field 0). The comparison now
>> fails on every boot and we always take the full CDCLK PLL
>> disable+re-enable path with the BIOS framebuffer actively scanning
>> out - exactly what this code was trying to avoid. On a Panther Lake
>> laptop (Arc B390, 8086:b080, eDP 3120x2080@120) this causes
>> "CPU pipe A FIFO underrun" during probe and persistent full-screen
>> scanout corruption for the first KMS client (the SDDM greeter);
>> the corruption lasts until the next full modeset.
>>
>> Only normalize the CD2X pipe select field on platforms where
>> bxt_cdclk_ctl() actually programs it, mirroring its DISPLAY_VER()
>> check.
>>
>> Fixes: 2ee8dbd880b1 ("drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL without a full PLL re-enable")
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Chang Jiong(常炯) <xspeed1989@gmail.com>
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8550
> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8569
> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8901
>
> The first one has a patch from Ville that is identical to this one.
>
> I'll try to kick CI to get this tested before merging.

Okay, the patch is against some stable kernel, not against the current
development tree. Please rebase on top of the drm-tip branch of the
drm-tip repository.

Thanks,
Jani.



>
>> ---
>> v2: No code changes. Resent with From matching Signed-off-by
>>     (v1 was sent from 304750714@qq.com, which is not on the
>>     Intel CI allowlist).
>>
>>  drivers/gpu/drm/i915/display/intel_cdclk.c | 6 ++++--
>>  1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index 7bc9b956554b..0438f5ac78c0 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -2366,8 +2366,10 @@ static void bxt_sanitize_cdclk(struct intel_display *display)
>>  	 * dividers both syncing to an active pipe, or asynchronously
>>  	 * (PIPE_NONE).
>>  	 */
>> -	cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
>> -	cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
>> +	if (DISPLAY_VER(display) < 30) {
>> +		cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
>> +		cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
>> +	}
>>  
>>  	if (cdctl != expected) {
>>  		if (DISPLAY_VER(display) < 20) {

-- 
Jani Nikula, Intel
Re: [PATCH v2] drm/i915/cdclk: Don't force cd2x pipe select on Xe3 in bxt_sanitize_cdclk()
Posted by Ville Syrjälä 1 month, 1 week ago 
On Wed, Aug 19, 2026 at 12:33:56PM +0300, Jani Nikula wrote:
> On Tue, 18 Aug 2026, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > On Sun, 16 Aug 2026, Chang Jiong(常炯) <xspeed1989@gmail.com> wrote:
> >> Since commit 2ee8dbd880b1 ("drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL
> >> without a full PLL re-enable") bxt_sanitize_cdclk() normalizes the
> >> CD2X pipe select field of the CDCLK_CTL readback to PIPE_NONE before
> >> comparing against the expected value.
> >>
> >> However bxt_cdclk_ctl() does not include the CD2X pipe select field
> >> at all on DISPLAY_VER() >= 30, so on Xe3 (PTL) the normalized
> >> readback (pipe field forced to the PIPE_NONE encoding, 0b111) can
> >> never match the expected value (pipe field 0). The comparison now
> >> fails on every boot and we always take the full CDCLK PLL
> >> disable+re-enable path with the BIOS framebuffer actively scanning
> >> out - exactly what this code was trying to avoid. On a Panther Lake
> >> laptop (Arc B390, 8086:b080, eDP 3120x2080@120) this causes
> >> "CPU pipe A FIFO underrun" during probe and persistent full-screen
> >> scanout corruption for the first KMS client (the SDDM greeter);
> >> the corruption lasts until the next full modeset.
> >>
> >> Only normalize the CD2X pipe select field on platforms where
> >> bxt_cdclk_ctl() actually programs it, mirroring its DISPLAY_VER()
> >> check.
> >>
> >> Fixes: 2ee8dbd880b1 ("drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL without a full PLL re-enable")
> >> Cc: stable@vger.kernel.org
> >> Signed-off-by: Chang Jiong(常炯) <xspeed1989@gmail.com>
> >
> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> > Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8550
> > Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8569
> > Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8901
> >
> > The first one has a patch from Ville that is identical to this one.
> >
> > I'll try to kick CI to get this tested before merging.
> 
> Okay, the patch is against some stable kernel, not against the current
> development tree. Please rebase on top of the drm-tip branch of the
> drm-tip repository.

I pushed my original fix and closed the other bugs as duplicates.

-- 
Ville Syrjälä
Intel
Re: [PATCH v2] drm/i915/cdclk: Don't force cd2x pipe select on Xe3 in bxt_sanitize_cdclk()
Posted by Zhefu Zhang 1 month, 1 week ago 
I hit the same bug independently on a Panther Lake laptop
(Xiaomi Book Pro 14 2026, 8086:b080, Xe3_LPD display 30 stepping B0).

Arch linux 7.1.8 stock reproduces the corruption with two
"CPU pipe A FIFO underrun" errors. With the same change applied on 7.1.8,
the panel is clean and the boot log has no FIFO underrun. Also verified
the same change on current drm-tip (b801f94c49ffdb0f65e37baf31d68570356d4983):
normal panel, no FIFO underrun.

Tested-by: Zhefu Zhang <a723356@gmail.com>

Patchew 2.1-devel-ea86937

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