To meet the specification requirement in the standard-mode bus frequency,
update the SCL counters as recommended by the design team.

IPQ5424 uses 32MHz source clock for the I2C and I2C is supported on both
RTL-hardened and firmware based SEs. The driver already provides SCL timing
parameters for a 32 MHz source clock, but the resulting I2C bus frequencies
do not meet the required specification on firmware-based SEs.

As recommended by the hardware design team, use a separate set of SCL
timing parameters for firmware-based SEs. Introduce a dedicated
frequency table and select the appropriate table based on the SE type.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
Changes in v2:
- Reworded the commit message to provide more background
- s/geni_i2c_clk_map_32mhz/geni_i2c_clk_map_32mhz_minicore/
- Link to v1: https://patch.msgid.link/20260811-ipq5424_i2c_scl_updates-v1-0-bddcb2ceebda@oss.qualcomm.com

To: Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com>
To: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
To: Andi Shyti <andi.shyti@kernel.org>
To: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
To: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
To: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konradybcio@kernel.org>
Cc: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
Cc: linux-i2c@vger.kernel.org
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

---
Kathiravan Thirumoorthy (2):
      i2c: qcom-geni: update frequency table to fix timing parameters
      i2c: qcom-geni: add I2C frequency table for 32 MHz firmware-based SEs

 drivers/i2c/busses/i2c-qcom-geni.c | 29 ++++++++++++++++++++---------
 include/linux/soc/qcom/geni-se.h   |  1 +
 2 files changed, 21 insertions(+), 9 deletions(-)
---
base-commit: 3d08ff75a47a3e7e2ab45a3bcab6723b4d906422
change-id: 20260808-ipq5424_i2c_scl_updates-f1696a0590fc

Best regards,
--  
Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>