As per the ARM GICv3 spec, the maintenance interrupt identified by
ICH_MISR_EL2.NP is asserted when it is enabled and no List register is
in pending state. This is further described in the document as "no List
registers with the State field set to 0b01 (pending)". By checking only
the pending bit of the LR (bit 62), KVM currently asserts the MI when
there are no LRs in "pending" or "pending and active" states.
Fix the detection logic to consider only the "pending" state.

Cc: stable@vger.kernel.org
Fixes: 96c2f03311de ("KVM: arm64: nv: Plumb handling of GICv3 EL2 accesses")
Signed-off-by: Kajetan Puchalski <kajetan.puchalski@arm.com>
---
 arch/arm64/kvm/vgic/vgic-v3-nested.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/kvm/vgic/vgic-v3-nested.c b/arch/arm64/kvm/vgic/vgic-v3-nested.c
index 5c69fa615823..e3e84d7f5ad5 100644
--- a/arch/arm64/kvm/vgic/vgic-v3-nested.c
+++ b/arch/arm64/kvm/vgic/vgic-v3-nested.c
@@ -152,7 +152,7 @@ static void vgic_compute_mi_state(struct kvm_vcpu *vcpu, struct mi_state *mi_sta
 			eisr |= BIT(i);
 		if (!(lr & ICH_LR_STATE))
 			elrsr |= BIT(i);
-		pend |= (lr & ICH_LR_PENDING_BIT);
+		pend |= (lr & ICH_LR_STATE) == ICH_LR_PENDING_BIT;
 	}
 
 	mi_state->eisr	= eisr;
-- 
2.51.0

On Mon, 10 Aug 2026 11:29:24 +0100, Kajetan Puchalski wrote:
> As per the ARM GICv3 spec, the maintenance interrupt identified by
> ICH_MISR_EL2.NP is asserted when it is enabled and no List register is
> in pending state. This is further described in the document as "no List
> registers with the State field set to 0b01 (pending)". By checking only
> the pending bit of the LR (bit 62), KVM currently asserts the MI when
> there are no LRs in "pending" or "pending and active" states.
> Fix the detection logic to consider only the "pending" state.
> 
> [...]

Applied to next, thanks!

[1/1] KVM: arm64: vgic: Fix detection of MI on no pending LR
      https://git.kernel.org/kvmarm/kvmarm/c/a342faadc5ac

--
Best,
Oliver

[Fixing up the initial recipient list...]

On Mon, 10 Aug 2026 11:29:24 +0100,
Kajetan Puchalski <kajetan.puchalski@arm.com> wrote:
> 
> As per the ARM GICv3 spec, the maintenance interrupt identified by
> ICH_MISR_EL2.NP is asserted when it is enabled and no List register is
> in pending state. This is further described in the document as "no List
> registers with the State field set to 0b01 (pending)". By checking only
> the pending bit of the LR (bit 62), KVM currently asserts the MI when
> there are no LRs in "pending" or "pending and active" states.
> Fix the detection logic to consider only the "pending" state.
> 
> Cc: stable@vger.kernel.org
> Fixes: 96c2f03311de ("KVM: arm64: nv: Plumb handling of GICv3 EL2 accesses")
> Signed-off-by: Kajetan Puchalski <kajetan.puchalski@arm.com>
> ---
>  arch/arm64/kvm/vgic/vgic-v3-nested.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/kvm/vgic/vgic-v3-nested.c b/arch/arm64/kvm/vgic/vgic-v3-nested.c
> index 5c69fa615823..e3e84d7f5ad5 100644
> --- a/arch/arm64/kvm/vgic/vgic-v3-nested.c
> +++ b/arch/arm64/kvm/vgic/vgic-v3-nested.c
> @@ -152,7 +152,7 @@ static void vgic_compute_mi_state(struct kvm_vcpu *vcpu, struct mi_state *mi_sta
>  			eisr |= BIT(i);
>  		if (!(lr & ICH_LR_STATE))
>  			elrsr |= BIT(i);
> -		pend |= (lr & ICH_LR_PENDING_BIT);
> +		pend |= (lr & ICH_LR_STATE) == ICH_LR_PENDING_BIT;
>  	}
>  
>  	mi_state->eisr	= eisr;

Thanks for catching this.

Reviewed-by: Marc Zyngier <maz@kernel.org>

	M.

-- 
Without deviation from the norm, progress is not possible.