MAINTAINERS | 9 + arch/riscv/Kconfig | 2 + arch/riscv/include/asm/hw_breakpoint.h | 299 +++++++ arch/riscv/include/asm/kdebug.h | 3 +- arch/riscv/include/asm/processor.h | 18 + arch/riscv/include/uapi/asm/ptrace.h | 53 ++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/hw_breakpoint.c | 677 ++++++++++++++++ arch/riscv/kernel/process.c | 5 + arch/riscv/kernel/ptrace.c | 507 ++++++++++++ arch/riscv/kernel/traps.c | 6 + include/uapi/linux/elf.h | 4 + tools/include/uapi/linux/elf.h | 2 + tools/testing/selftests/breakpoints/Makefile | 5 + .../breakpoints/breakpoint_test_riscv.c | 765 ++++++++++++++++++ 15 files changed, 2355 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/hw_breakpoint.h create mode 100644 arch/riscv/kernel/hw_breakpoint.c create mode 100644 tools/testing/selftests/breakpoints/breakpoint_test_riscv.c
This patchset adds support for hardware breakpoints and watchpoints in the
RISC-V architecture. The framework is built on top of the perf subsystem and
the SBI debug trigger extension (Sdtrig).
v6 extends v5 with two new patches:
- ptrace support: debuggers can now set and query hardware debug triggers
through the standard PTRACE_GETREGSET/SETREGSET interface using new
NT_RISCV_HW_BREAK/WATCH note types. A simpler PTRACE_GETHBPREGS/SETHBPREGS
request pair is also provided for direct single-trigger access without going
through the regset machinery. Thread flush/copy hooks are wired up so
per-task breakpoints are cleaned up across fork/exec.
- Extended selftest: the existing perf_event-based selftest is extended to
also exercise the new ptrace GETREGSET/SETREGSET regset path and the raw
PTRACE_GETHBPREGS/SETHBPREGS interface.
Single stepping is ready and test but to follow this patch set.
Virtualization of debug triggers are pending
The SBI debug trigger extension is specified in Chapter 19 of the SBI
specification:
https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0/riscv-sbi.pdf
The Sdtrig ISA is part of the RISC-V debug specification:
https://github.com/riscv/riscv-debug-spec
Changes from v5:
- Rebased to v7.2-rc6
- Simplified Macros in hw_breakpoint.h
- Took care of the review comments
- Added ptrace support for hardware break/watchpoints (new patch)
- PTRACE_GETREGSET/SETREGSET via NT_RISCV_HW_BREAK / NT_RISCV_HW_WATCH
- PTRACE_GETHBPREGS / SETHBPREGS for direct single-trigger access
- HAVE_MIXED_BREAKPOINTS_REGS selected (break/watch share trigger pool)
- flush_ptrace_hw_breakpoint / ptrace_hw_copy_thread wired up
- Extended selftest to cover ptrace-based hw break/watchpoint paths (new patch)
Changes from v4:
- Rebased to v7.2-rc4
- Fixed rv32 build error
- Added pr_fmt to print KBUILD_MODNAME
- Changed type of shmem_pa to phys_addr_t
- Use per_cpu_ptr_to_phys instead of __pa for per-cpu allocated memory
- Print successful registration/unregistration message when no error
- Added RISC-V DEBUGGING section in MAINTAINERS and added myself as maintainer
- Fixed warnings from checkpatch.pl --strict run
Changes from v3:
- Rebased to v7.1-rc3
- For watchpoints, check tdata1.hit via SBI_EXT_DBTR_TRIG_READ and keep
STVAL-based matching as fallback
- Improved watchpoint matching when STVAL reports the lowest accessed address
for wider memory accesses
- Program execute breakpoints with SIZE=0 (match any size) to avoid misses
with 16-bit/compressed instruction addresses
- Updated selftest to avoid deadlock by replacing unbounded sem_wait() with
sem_timedwait() timeout handling
- Updated selftest breakpoint function so it cannot be inlined or optimized away
Changes from v2:
- Rebased to v7.0-rc1
- Fixed warnings from checkpatch.pl --strict run
Changes from v1:
- The patch adding the SBI extension and function IDs is already merged; this
series builds on top of that
- Added breakpoint selftest in tools/testing/selftests/breakpoints/
How to use:
~~~~~~~~~~~
OpenSBI:
https://github.com/riscv-software-src/opensbi.git
QEMU:
https://github.com/qemu/qemu.git
Linux Kernel:
Apply these patches on top of v7.2-rc6.
How to test:
~~~~~~~~~~~
From the Linux kernel directory, first install the UAPI headers (required on a
fresh tree so the compiler can locate <asm/ptrace.h> and the new
NT_RISCV_HW_BREAK/WATCH definitions via KHDR_INCLUDES):
make headers
Then build the selftest:
make -C tools/testing/selftests/breakpoints/
This produces breakpoint_test_riscv under the same directory. Load it on the
target and run. Sample output:
# /apps/breakpoint_test_riscv
# [perf_event]: Breakpoint test passed!
# [perf_event]: Watchpoint test passed!
# [ptrace]: Breakpoint test passed!
# ptrace(PTRACE_GETREGSET): Number of watchpoints: 2
# ptrace(PTRACE_GETREGSet): addr: 0x82888 control: 0x8080
# [ptrace]: Watchpoint test passed!
# [hbpregs] breakpoint readback: addr=0x10472 type=4 len=4 ctrl=0
# [hbpregs]: Breakpoint test passed!
# [hbpregs] watchpoint readback: addr=0x82888 type=2 len=8 ctrl=0
# [hbpregs]: Watchpoint test passed!
Himanshu Chauhan (5):
riscv: Introduce support for hardware break/watchpoints
riscv: Add breakpoint and watchpoint test for riscv
riscv: ptrace support for hardware break/watchpoints
selftests/breakpoints: extend riscv test for ptrace hw
break/watchpoints
MAINTAINERS: Add entry for RISC-V Debugging
MAINTAINERS | 9 +
arch/riscv/Kconfig | 2 +
arch/riscv/include/asm/hw_breakpoint.h | 299 +++++++
arch/riscv/include/asm/kdebug.h | 3 +-
arch/riscv/include/asm/processor.h | 18 +
arch/riscv/include/uapi/asm/ptrace.h | 53 ++
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/hw_breakpoint.c | 677 ++++++++++++++++
arch/riscv/kernel/process.c | 5 +
arch/riscv/kernel/ptrace.c | 507 ++++++++++++
arch/riscv/kernel/traps.c | 6 +
include/uapi/linux/elf.h | 4 +
tools/include/uapi/linux/elf.h | 2 +
tools/testing/selftests/breakpoints/Makefile | 5 +
.../breakpoints/breakpoint_test_riscv.c | 765 ++++++++++++++++++
15 files changed, 2355 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/include/asm/hw_breakpoint.h
create mode 100644 arch/riscv/kernel/hw_breakpoint.c
create mode 100644 tools/testing/selftests/breakpoints/breakpoint_test_riscv.c
--
2.43.0
On Mon, Aug 3, 2026 at 9:49 AM Himanshu Chauhan <himanshu.chauhan@oss.qualcomm.com> wrote: > > This patchset adds support for hardware breakpoints and watchpoints in the > RISC-V architecture. The framework is built on top of the perf subsystem and > the SBI debug trigger extension (Sdtrig). > > v6 extends v5 with two new patches: > > - ptrace support: debuggers can now set and query hardware debug triggers > through the standard PTRACE_GETREGSET/SETREGSET interface using new > NT_RISCV_HW_BREAK/WATCH note types. A simpler PTRACE_GETHBPREGS/SETHBPREGS > request pair is also provided for direct single-trigger access without going > through the regset machinery. Thread flush/copy hooks are wired up so > per-task breakpoints are cleaned up across fork/exec. > > - Extended selftest: the existing perf_event-based selftest is extended to > also exercise the new ptrace GETREGSET/SETREGSET regset path and the raw > PTRACE_GETHBPREGS/SETHBPREGS interface. I would recoment addaping `tools/testing/selftests/breakpoints/breakpoint_test_arm64.c` as a test. I set up a test repository here https://github.com/Mr-Bossman/dbtr-buildroot for anyone else to test this set. Unfortunatly this set fails `perf test 15 16 17 18`. I would like those tests to pass before accepting this set. My set addresses the perf failures which is why it is more complicated. I would highly recommend basing your set off of it as it fixes many of the issues that I commented on in V5. The first two commits in my series are refactoring duplicate code, and can technically be dropped. Even if you don't go forward with using my set, I would at least recommend taking a look at it, especially `riscv: ptrace: Add hw breakpoint regset` and `riscv: ptrace: Add hw breakpoint support` as they are significantly simpler. https://github.com/Mr-Bossman/linux/commits/dev/jesse/sdtrig-rebase/ Thanks, Jesse Taube > Single stepping is ready and test but to follow this patch set. > Virtualization of debug triggers are pending > > The SBI debug trigger extension is specified in Chapter 19 of the SBI > specification: > https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0/riscv-sbi.pdf > > The Sdtrig ISA is part of the RISC-V debug specification: > https://github.com/riscv/riscv-debug-spec > > Changes from v5: > - Rebased to v7.2-rc6 > - Simplified Macros in hw_breakpoint.h > - Took care of the review comments > - Added ptrace support for hardware break/watchpoints (new patch) > - PTRACE_GETREGSET/SETREGSET via NT_RISCV_HW_BREAK / NT_RISCV_HW_WATCH > - PTRACE_GETHBPREGS / SETHBPREGS for direct single-trigger access > - HAVE_MIXED_BREAKPOINTS_REGS selected (break/watch share trigger pool) > - flush_ptrace_hw_breakpoint / ptrace_hw_copy_thread wired up > - Extended selftest to cover ptrace-based hw break/watchpoint paths (new patch) > > Changes from v4: > - Rebased to v7.2-rc4 > - Fixed rv32 build error > - Added pr_fmt to print KBUILD_MODNAME > - Changed type of shmem_pa to phys_addr_t > - Use per_cpu_ptr_to_phys instead of __pa for per-cpu allocated memory > - Print successful registration/unregistration message when no error > - Added RISC-V DEBUGGING section in MAINTAINERS and added myself as maintainer > - Fixed warnings from checkpatch.pl --strict run > > Changes from v3: > - Rebased to v7.1-rc3 > - For watchpoints, check tdata1.hit via SBI_EXT_DBTR_TRIG_READ and keep > STVAL-based matching as fallback > - Improved watchpoint matching when STVAL reports the lowest accessed address > for wider memory accesses > - Program execute breakpoints with SIZE=0 (match any size) to avoid misses > with 16-bit/compressed instruction addresses > - Updated selftest to avoid deadlock by replacing unbounded sem_wait() with > sem_timedwait() timeout handling > - Updated selftest breakpoint function so it cannot be inlined or optimized away > > Changes from v2: > - Rebased to v7.0-rc1 > - Fixed warnings from checkpatch.pl --strict run > > Changes from v1: > - The patch adding the SBI extension and function IDs is already merged; this > series builds on top of that > - Added breakpoint selftest in tools/testing/selftests/breakpoints/ > > How to use: > ~~~~~~~~~~~ > OpenSBI: > https://github.com/riscv-software-src/opensbi.git > > QEMU: > https://github.com/qemu/qemu.git > > Linux Kernel: > Apply these patches on top of v7.2-rc6. > > How to test: > ~~~~~~~~~~~ > From the Linux kernel directory, first install the UAPI headers (required on a > fresh tree so the compiler can locate <asm/ptrace.h> and the new > NT_RISCV_HW_BREAK/WATCH definitions via KHDR_INCLUDES): > > make headers > > Then build the selftest: > > make -C tools/testing/selftests/breakpoints/ > > This produces breakpoint_test_riscv under the same directory. Load it on the > target and run. Sample output: > > # /apps/breakpoint_test_riscv > # [perf_event]: Breakpoint test passed! > # [perf_event]: Watchpoint test passed! > # [ptrace]: Breakpoint test passed! > # ptrace(PTRACE_GETREGSET): Number of watchpoints: 2 > # ptrace(PTRACE_GETREGSet): addr: 0x82888 control: 0x8080 > # [ptrace]: Watchpoint test passed! > # [hbpregs] breakpoint readback: addr=0x10472 type=4 len=4 ctrl=0 > # [hbpregs]: Breakpoint test passed! > # [hbpregs] watchpoint readback: addr=0x82888 type=2 len=8 ctrl=0 > # [hbpregs]: Watchpoint test passed! > > Himanshu Chauhan (5): > riscv: Introduce support for hardware break/watchpoints > riscv: Add breakpoint and watchpoint test for riscv > riscv: ptrace support for hardware break/watchpoints > selftests/breakpoints: extend riscv test for ptrace hw > break/watchpoints > MAINTAINERS: Add entry for RISC-V Debugging > > MAINTAINERS | 9 + > arch/riscv/Kconfig | 2 + > arch/riscv/include/asm/hw_breakpoint.h | 299 +++++++ > arch/riscv/include/asm/kdebug.h | 3 +- > arch/riscv/include/asm/processor.h | 18 + > arch/riscv/include/uapi/asm/ptrace.h | 53 ++ > arch/riscv/kernel/Makefile | 1 + > arch/riscv/kernel/hw_breakpoint.c | 677 ++++++++++++++++ > arch/riscv/kernel/process.c | 5 + > arch/riscv/kernel/ptrace.c | 507 ++++++++++++ > arch/riscv/kernel/traps.c | 6 + > include/uapi/linux/elf.h | 4 + > tools/include/uapi/linux/elf.h | 2 + > tools/testing/selftests/breakpoints/Makefile | 5 + > .../breakpoints/breakpoint_test_riscv.c | 765 ++++++++++++++++++ > 15 files changed, 2355 insertions(+), 1 deletion(-) > create mode 100644 arch/riscv/include/asm/hw_breakpoint.h > create mode 100644 arch/riscv/kernel/hw_breakpoint.c > create mode 100644 tools/testing/selftests/breakpoints/breakpoint_test_riscv.c > > -- > 2.43.0 >
On Tue, Aug 4, 2026 at 10:42 PM Jesse Taube <jtaubepe@redhat.com> wrote: > > On Mon, Aug 3, 2026 at 9:49 AM Himanshu Chauhan > <himanshu.chauhan@oss.qualcomm.com> wrote: > > > > This patchset adds support for hardware breakpoints and watchpoints in the > > RISC-V architecture. The framework is built on top of the perf subsystem and > > the SBI debug trigger extension (Sdtrig). > > > > v6 extends v5 with two new patches: > > > > - ptrace support: debuggers can now set and query hardware debug triggers > > through the standard PTRACE_GETREGSET/SETREGSET interface using new > > NT_RISCV_HW_BREAK/WATCH note types. A simpler PTRACE_GETHBPREGS/SETHBPREGS > > request pair is also provided for direct single-trigger access without going > > through the regset machinery. Thread flush/copy hooks are wired up so > > per-task breakpoints are cleaned up across fork/exec. > > > > - Extended selftest: the existing perf_event-based selftest is extended to > > also exercise the new ptrace GETREGSET/SETREGSET regset path and the raw > > PTRACE_GETHBPREGS/SETHBPREGS interface. > > I would recoment addaping > `tools/testing/selftests/breakpoints/breakpoint_test_arm64.c` as a > test. > I set up a test repository here > https://github.com/Mr-Bossman/dbtr-buildroot for anyone else to test > this set. > > Unfortunatly this set fails `perf test 15 16 17 18`. I would like > those tests to pass > before accepting this set. My set addresses the perf failures which is why it is > more complicated. > > I would highly recommend basing your set off of it as it fixes many of > the issues that > I commented on in V5. The first two commits in my series are > refactoring duplicate code, > and can technically be dropped. Even if you don't go forward with using my set, > I would at least recommend taking a look at it, especially > `riscv: ptrace: Add hw breakpoint regset` > and > `riscv: ptrace: Add hw breakpoint support` > as they are significantly simpler. > All that is taken care of. There is a problem with icount triggers in Qemu. Once I fix that, I will send v7 and It will contain single stepping. Regards Himanshu > https://github.com/Mr-Bossman/linux/commits/dev/jesse/sdtrig-rebase/ > > Thanks, > Jesse Taube > > > Single stepping is ready and test but to follow this patch set. > > Virtualization of debug triggers are pending > > > > The SBI debug trigger extension is specified in Chapter 19 of the SBI > > specification: > > https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0/riscv-sbi.pdf > > > > The Sdtrig ISA is part of the RISC-V debug specification: > > https://github.com/riscv/riscv-debug-spec > > > > Changes from v5: > > - Rebased to v7.2-rc6 > > - Simplified Macros in hw_breakpoint.h > > - Took care of the review comments > > - Added ptrace support for hardware break/watchpoints (new patch) > > - PTRACE_GETREGSET/SETREGSET via NT_RISCV_HW_BREAK / NT_RISCV_HW_WATCH > > - PTRACE_GETHBPREGS / SETHBPREGS for direct single-trigger access > > - HAVE_MIXED_BREAKPOINTS_REGS selected (break/watch share trigger pool) > > - flush_ptrace_hw_breakpoint / ptrace_hw_copy_thread wired up > > - Extended selftest to cover ptrace-based hw break/watchpoint paths (new patch) > > > > Changes from v4: > > - Rebased to v7.2-rc4 > > - Fixed rv32 build error > > - Added pr_fmt to print KBUILD_MODNAME > > - Changed type of shmem_pa to phys_addr_t > > - Use per_cpu_ptr_to_phys instead of __pa for per-cpu allocated memory > > - Print successful registration/unregistration message when no error > > - Added RISC-V DEBUGGING section in MAINTAINERS and added myself as maintainer > > - Fixed warnings from checkpatch.pl --strict run > > > > Changes from v3: > > - Rebased to v7.1-rc3 > > - For watchpoints, check tdata1.hit via SBI_EXT_DBTR_TRIG_READ and keep > > STVAL-based matching as fallback > > - Improved watchpoint matching when STVAL reports the lowest accessed address > > for wider memory accesses > > - Program execute breakpoints with SIZE=0 (match any size) to avoid misses > > with 16-bit/compressed instruction addresses > > - Updated selftest to avoid deadlock by replacing unbounded sem_wait() with > > sem_timedwait() timeout handling > > - Updated selftest breakpoint function so it cannot be inlined or optimized away > > > > Changes from v2: > > - Rebased to v7.0-rc1 > > - Fixed warnings from checkpatch.pl --strict run > > > > Changes from v1: > > - The patch adding the SBI extension and function IDs is already merged; this > > series builds on top of that > > - Added breakpoint selftest in tools/testing/selftests/breakpoints/ > > > > How to use: > > ~~~~~~~~~~~ > > OpenSBI: > > https://github.com/riscv-software-src/opensbi.git > > > > QEMU: > > https://github.com/qemu/qemu.git > > > > Linux Kernel: > > Apply these patches on top of v7.2-rc6. > > > > How to test: > > ~~~~~~~~~~~ > > From the Linux kernel directory, first install the UAPI headers (required on a > > fresh tree so the compiler can locate <asm/ptrace.h> and the new > > NT_RISCV_HW_BREAK/WATCH definitions via KHDR_INCLUDES): > > > > make headers > > > > Then build the selftest: > > > > make -C tools/testing/selftests/breakpoints/ > > > > This produces breakpoint_test_riscv under the same directory. Load it on the > > target and run. Sample output: > > > > # /apps/breakpoint_test_riscv > > # [perf_event]: Breakpoint test passed! > > # [perf_event]: Watchpoint test passed! > > # [ptrace]: Breakpoint test passed! > > # ptrace(PTRACE_GETREGSET): Number of watchpoints: 2 > > # ptrace(PTRACE_GETREGSet): addr: 0x82888 control: 0x8080 > > # [ptrace]: Watchpoint test passed! > > # [hbpregs] breakpoint readback: addr=0x10472 type=4 len=4 ctrl=0 > > # [hbpregs]: Breakpoint test passed! > > # [hbpregs] watchpoint readback: addr=0x82888 type=2 len=8 ctrl=0 > > # [hbpregs]: Watchpoint test passed! > > > > Himanshu Chauhan (5): > > riscv: Introduce support for hardware break/watchpoints > > riscv: Add breakpoint and watchpoint test for riscv > > riscv: ptrace support for hardware break/watchpoints > > selftests/breakpoints: extend riscv test for ptrace hw > > break/watchpoints > > MAINTAINERS: Add entry for RISC-V Debugging > > > > MAINTAINERS | 9 + > > arch/riscv/Kconfig | 2 + > > arch/riscv/include/asm/hw_breakpoint.h | 299 +++++++ > > arch/riscv/include/asm/kdebug.h | 3 +- > > arch/riscv/include/asm/processor.h | 18 + > > arch/riscv/include/uapi/asm/ptrace.h | 53 ++ > > arch/riscv/kernel/Makefile | 1 + > > arch/riscv/kernel/hw_breakpoint.c | 677 ++++++++++++++++ > > arch/riscv/kernel/process.c | 5 + > > arch/riscv/kernel/ptrace.c | 507 ++++++++++++ > > arch/riscv/kernel/traps.c | 6 + > > include/uapi/linux/elf.h | 4 + > > tools/include/uapi/linux/elf.h | 2 + > > tools/testing/selftests/breakpoints/Makefile | 5 + > > .../breakpoints/breakpoint_test_riscv.c | 765 ++++++++++++++++++ > > 15 files changed, 2355 insertions(+), 1 deletion(-) > > create mode 100644 arch/riscv/include/asm/hw_breakpoint.h > > create mode 100644 arch/riscv/kernel/hw_breakpoint.c > > create mode 100644 tools/testing/selftests/breakpoints/breakpoint_test_riscv.c > > > > -- > > 2.43.0 > > > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Fri, Aug 07, 2026 at 01:30:09PM +0530, Himanshu Chauhan wrote: > On Tue, Aug 4, 2026 at 10:42 PM Jesse Taube <jtaubepe@redhat.com> wrote: > > > > On Mon, Aug 3, 2026 at 9:49 AM Himanshu Chauhan > > <himanshu.chauhan@oss.qualcomm.com> wrote: > > > > > > This patchset adds support for hardware breakpoints and watchpoints in the > > > RISC-V architecture. The framework is built on top of the perf subsystem and > > > the SBI debug trigger extension (Sdtrig). > > > > > > v6 extends v5 with two new patches: > > > > > > - ptrace support: debuggers can now set and query hardware debug triggers > > > through the standard PTRACE_GETREGSET/SETREGSET interface using new > > > NT_RISCV_HW_BREAK/WATCH note types. A simpler PTRACE_GETHBPREGS/SETHBPREGS > > > request pair is also provided for direct single-trigger access without going > > > through the regset machinery. Thread flush/copy hooks are wired up so > > > per-task breakpoints are cleaned up across fork/exec. > > > > > > - Extended selftest: the existing perf_event-based selftest is extended to > > > also exercise the new ptrace GETREGSET/SETREGSET regset path and the raw > > > PTRACE_GETHBPREGS/SETHBPREGS interface. > > > > I would recoment addaping > > `tools/testing/selftests/breakpoints/breakpoint_test_arm64.c` as a > > test. > > I set up a test repository here > > https://github.com/Mr-Bossman/dbtr-buildroot for anyone else to test > > this set. > > > > Unfortunatly this set fails `perf test 15 16 17 18`. I would like > > those tests to pass > > before accepting this set. My set addresses the perf failures which is why it is > > more complicated. > > > > I would highly recommend basing your set off of it as it fixes many of > > the issues that > > I commented on in V5. The first two commits in my series are > > refactoring duplicate code, > > and can technically be dropped. Even if you don't go forward with using my set, > > I would at least recommend taking a look at it, especially > > `riscv: ptrace: Add hw breakpoint regset` > > and > > `riscv: ptrace: Add hw breakpoint support` > > as they are significantly simpler. > > > > All that is taken care of. There is a problem with icount triggers in > Qemu. Once I fix that, I will send v7 and It will contain single > stepping. > > Regards > Himanshu Why did you decide to renew this patch series without pulling in Jesse's patches? - Charlie > > > https://github.com/Mr-Bossman/linux/commits/dev/jesse/sdtrig-rebase/ > > > > Thanks, > > Jesse Taube > > > > > Single stepping is ready and test but to follow this patch set. > > > Virtualization of debug triggers are pending > > > > > > The SBI debug trigger extension is specified in Chapter 19 of the SBI > > > specification: > > > https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0/riscv-sbi.pdf > > > > > > The Sdtrig ISA is part of the RISC-V debug specification: > > > https://github.com/riscv/riscv-debug-spec > > > > > > Changes from v5: > > > - Rebased to v7.2-rc6 > > > - Simplified Macros in hw_breakpoint.h > > > - Took care of the review comments > > > - Added ptrace support for hardware break/watchpoints (new patch) > > > - PTRACE_GETREGSET/SETREGSET via NT_RISCV_HW_BREAK / NT_RISCV_HW_WATCH > > > - PTRACE_GETHBPREGS / SETHBPREGS for direct single-trigger access > > > - HAVE_MIXED_BREAKPOINTS_REGS selected (break/watch share trigger pool) > > > - flush_ptrace_hw_breakpoint / ptrace_hw_copy_thread wired up > > > - Extended selftest to cover ptrace-based hw break/watchpoint paths (new patch) > > > > > > Changes from v4: > > > - Rebased to v7.2-rc4 > > > - Fixed rv32 build error > > > - Added pr_fmt to print KBUILD_MODNAME > > > - Changed type of shmem_pa to phys_addr_t > > > - Use per_cpu_ptr_to_phys instead of __pa for per-cpu allocated memory > > > - Print successful registration/unregistration message when no error > > > - Added RISC-V DEBUGGING section in MAINTAINERS and added myself as maintainer > > > - Fixed warnings from checkpatch.pl --strict run > > > > > > Changes from v3: > > > - Rebased to v7.1-rc3 > > > - For watchpoints, check tdata1.hit via SBI_EXT_DBTR_TRIG_READ and keep > > > STVAL-based matching as fallback > > > - Improved watchpoint matching when STVAL reports the lowest accessed address > > > for wider memory accesses > > > - Program execute breakpoints with SIZE=0 (match any size) to avoid misses > > > with 16-bit/compressed instruction addresses > > > - Updated selftest to avoid deadlock by replacing unbounded sem_wait() with > > > sem_timedwait() timeout handling > > > - Updated selftest breakpoint function so it cannot be inlined or optimized away > > > > > > Changes from v2: > > > - Rebased to v7.0-rc1 > > > - Fixed warnings from checkpatch.pl --strict run > > > > > > Changes from v1: > > > - The patch adding the SBI extension and function IDs is already merged; this > > > series builds on top of that > > > - Added breakpoint selftest in tools/testing/selftests/breakpoints/ > > > > > > How to use: > > > ~~~~~~~~~~~ > > > OpenSBI: > > > https://github.com/riscv-software-src/opensbi.git > > > > > > QEMU: > > > https://github.com/qemu/qemu.git > > > > > > Linux Kernel: > > > Apply these patches on top of v7.2-rc6. > > > > > > How to test: > > > ~~~~~~~~~~~ > > > From the Linux kernel directory, first install the UAPI headers (required on a > > > fresh tree so the compiler can locate <asm/ptrace.h> and the new > > > NT_RISCV_HW_BREAK/WATCH definitions via KHDR_INCLUDES): > > > > > > make headers > > > > > > Then build the selftest: > > > > > > make -C tools/testing/selftests/breakpoints/ > > > > > > This produces breakpoint_test_riscv under the same directory. Load it on the > > > target and run. Sample output: > > > > > > # /apps/breakpoint_test_riscv > > > # [perf_event]: Breakpoint test passed! > > > # [perf_event]: Watchpoint test passed! > > > # [ptrace]: Breakpoint test passed! > > > # ptrace(PTRACE_GETREGSET): Number of watchpoints: 2 > > > # ptrace(PTRACE_GETREGSet): addr: 0x82888 control: 0x8080 > > > # [ptrace]: Watchpoint test passed! > > > # [hbpregs] breakpoint readback: addr=0x10472 type=4 len=4 ctrl=0 > > > # [hbpregs]: Breakpoint test passed! > > > # [hbpregs] watchpoint readback: addr=0x82888 type=2 len=8 ctrl=0 > > > # [hbpregs]: Watchpoint test passed! > > > > > > Himanshu Chauhan (5): > > > riscv: Introduce support for hardware break/watchpoints > > > riscv: Add breakpoint and watchpoint test for riscv > > > riscv: ptrace support for hardware break/watchpoints > > > selftests/breakpoints: extend riscv test for ptrace hw > > > break/watchpoints > > > MAINTAINERS: Add entry for RISC-V Debugging > > > > > > MAINTAINERS | 9 + > > > arch/riscv/Kconfig | 2 + > > > arch/riscv/include/asm/hw_breakpoint.h | 299 +++++++ > > > arch/riscv/include/asm/kdebug.h | 3 +- > > > arch/riscv/include/asm/processor.h | 18 + > > > arch/riscv/include/uapi/asm/ptrace.h | 53 ++ > > > arch/riscv/kernel/Makefile | 1 + > > > arch/riscv/kernel/hw_breakpoint.c | 677 ++++++++++++++++ > > > arch/riscv/kernel/process.c | 5 + > > > arch/riscv/kernel/ptrace.c | 507 ++++++++++++ > > > arch/riscv/kernel/traps.c | 6 + > > > include/uapi/linux/elf.h | 4 + > > > tools/include/uapi/linux/elf.h | 2 + > > > tools/testing/selftests/breakpoints/Makefile | 5 + > > > .../breakpoints/breakpoint_test_riscv.c | 765 ++++++++++++++++++ > > > 15 files changed, 2355 insertions(+), 1 deletion(-) > > > create mode 100644 arch/riscv/include/asm/hw_breakpoint.h > > > create mode 100644 arch/riscv/kernel/hw_breakpoint.c > > > create mode 100644 tools/testing/selftests/breakpoints/breakpoint_test_riscv.c > > > > > > -- > > > 2.43.0 > > > > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv
Hi Charlie, On Wed, Sep 16, 2026 at 10:18 AM Charlie Jenkins <thecharlesjenkins@gmail.com> wrote: > > On Fri, Aug 07, 2026 at 01:30:09PM +0530, Himanshu Chauhan wrote: > > On Tue, Aug 4, 2026 at 10:42 PM Jesse Taube <jtaubepe@redhat.com> wrote: > > > > > > On Mon, Aug 3, 2026 at 9:49 AM Himanshu Chauhan > > > <himanshu.chauhan@oss.qualcomm.com> wrote: > > > > > > > > This patchset adds support for hardware breakpoints and watchpoints in the > > > > RISC-V architecture. The framework is built on top of the perf subsystem and > > > > the SBI debug trigger extension (Sdtrig). > > > > > > > > v6 extends v5 with two new patches: > > > > > > > > - ptrace support: debuggers can now set and query hardware debug triggers > > > > through the standard PTRACE_GETREGSET/SETREGSET interface using new > > > > NT_RISCV_HW_BREAK/WATCH note types. A simpler PTRACE_GETHBPREGS/SETHBPREGS > > > > request pair is also provided for direct single-trigger access without going > > > > through the regset machinery. Thread flush/copy hooks are wired up so > > > > per-task breakpoints are cleaned up across fork/exec. > > > > > > > > - Extended selftest: the existing perf_event-based selftest is extended to > > > > also exercise the new ptrace GETREGSET/SETREGSET regset path and the raw > > > > PTRACE_GETHBPREGS/SETHBPREGS interface. > > > > > > I would recoment addaping > > > `tools/testing/selftests/breakpoints/breakpoint_test_arm64.c` as a > > > test. > > > I set up a test repository here > > > https://github.com/Mr-Bossman/dbtr-buildroot for anyone else to test > > > this set. > > > > > > Unfortunatly this set fails `perf test 15 16 17 18`. I would like > > > those tests to pass > > > before accepting this set. My set addresses the perf failures which is why it is > > > more complicated. > > > > > > I would highly recommend basing your set off of it as it fixes many of > > > the issues that > > > I commented on in V5. The first two commits in my series are > > > refactoring duplicate code, > > > and can technically be dropped. Even if you don't go forward with using my set, > > > I would at least recommend taking a look at it, especially > > > `riscv: ptrace: Add hw breakpoint regset` > > > and > > > `riscv: ptrace: Add hw breakpoint support` > > > as they are significantly simpler. > > > > > > > All that is taken care of. There is a problem with icount triggers in > > Qemu. Once I fix that, I will send v7 and It will contain single > > stepping. > > > > Regards > > Himanshu > > Why did you decide to renew this patch series without pulling in Jesse's > patches? > I started this patch series long back starting from drafting of SBI DBTR specification and PoC implementation. I had planned to add support in a staged manner but Jesse came and hijacked the patch series without intimating or consulting me. I had later patches with me developed well before Jesse sent the hijacked series. Then later, Jesse abandoned the series with a lot of issues still to be fixed. I picked it up again and implemented it in a proper way. I am still doing it in a staged manner. More follow up patches will come with due credits. Do you have any concerns? Regards Himanshu > - Charlie > > > > > > https://github.com/Mr-Bossman/linux/commits/dev/jesse/sdtrig-rebase/ > > > > > > Thanks, > > > Jesse Taube > > > > > > > Single stepping is ready and test but to follow this patch set. > > > > Virtualization of debug triggers are pending > > > > > > > > The SBI debug trigger extension is specified in Chapter 19 of the SBI > > > > specification: > > > > https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0/riscv-sbi.pdf > > > > > > > > The Sdtrig ISA is part of the RISC-V debug specification: > > > > https://github.com/riscv/riscv-debug-spec > > > > > > > > Changes from v5: > > > > - Rebased to v7.2-rc6 > > > > - Simplified Macros in hw_breakpoint.h > > > > - Took care of the review comments > > > > - Added ptrace support for hardware break/watchpoints (new patch) > > > > - PTRACE_GETREGSET/SETREGSET via NT_RISCV_HW_BREAK / NT_RISCV_HW_WATCH > > > > - PTRACE_GETHBPREGS / SETHBPREGS for direct single-trigger access > > > > - HAVE_MIXED_BREAKPOINTS_REGS selected (break/watch share trigger pool) > > > > - flush_ptrace_hw_breakpoint / ptrace_hw_copy_thread wired up > > > > - Extended selftest to cover ptrace-based hw break/watchpoint paths (new patch) > > > > > > > > Changes from v4: > > > > - Rebased to v7.2-rc4 > > > > - Fixed rv32 build error > > > > - Added pr_fmt to print KBUILD_MODNAME > > > > - Changed type of shmem_pa to phys_addr_t > > > > - Use per_cpu_ptr_to_phys instead of __pa for per-cpu allocated memory > > > > - Print successful registration/unregistration message when no error > > > > - Added RISC-V DEBUGGING section in MAINTAINERS and added myself as maintainer > > > > - Fixed warnings from checkpatch.pl --strict run > > > > > > > > Changes from v3: > > > > - Rebased to v7.1-rc3 > > > > - For watchpoints, check tdata1.hit via SBI_EXT_DBTR_TRIG_READ and keep > > > > STVAL-based matching as fallback > > > > - Improved watchpoint matching when STVAL reports the lowest accessed address > > > > for wider memory accesses > > > > - Program execute breakpoints with SIZE=0 (match any size) to avoid misses > > > > with 16-bit/compressed instruction addresses > > > > - Updated selftest to avoid deadlock by replacing unbounded sem_wait() with > > > > sem_timedwait() timeout handling > > > > - Updated selftest breakpoint function so it cannot be inlined or optimized away > > > > > > > > Changes from v2: > > > > - Rebased to v7.0-rc1 > > > > - Fixed warnings from checkpatch.pl --strict run > > > > > > > > Changes from v1: > > > > - The patch adding the SBI extension and function IDs is already merged; this > > > > series builds on top of that > > > > - Added breakpoint selftest in tools/testing/selftests/breakpoints/ > > > > > > > > How to use: > > > > ~~~~~~~~~~~ > > > > OpenSBI: > > > > https://github.com/riscv-software-src/opensbi.git > > > > > > > > QEMU: > > > > https://github.com/qemu/qemu.git > > > > > > > > Linux Kernel: > > > > Apply these patches on top of v7.2-rc6. > > > > > > > > How to test: > > > > ~~~~~~~~~~~ > > > > From the Linux kernel directory, first install the UAPI headers (required on a > > > > fresh tree so the compiler can locate <asm/ptrace.h> and the new > > > > NT_RISCV_HW_BREAK/WATCH definitions via KHDR_INCLUDES): > > > > > > > > make headers > > > > > > > > Then build the selftest: > > > > > > > > make -C tools/testing/selftests/breakpoints/ > > > > > > > > This produces breakpoint_test_riscv under the same directory. Load it on the > > > > target and run. Sample output: > > > > > > > > # /apps/breakpoint_test_riscv > > > > # [perf_event]: Breakpoint test passed! > > > > # [perf_event]: Watchpoint test passed! > > > > # [ptrace]: Breakpoint test passed! > > > > # ptrace(PTRACE_GETREGSET): Number of watchpoints: 2 > > > > # ptrace(PTRACE_GETREGSet): addr: 0x82888 control: 0x8080 > > > > # [ptrace]: Watchpoint test passed! > > > > # [hbpregs] breakpoint readback: addr=0x10472 type=4 len=4 ctrl=0 > > > > # [hbpregs]: Breakpoint test passed! > > > > # [hbpregs] watchpoint readback: addr=0x82888 type=2 len=8 ctrl=0 > > > > # [hbpregs]: Watchpoint test passed! > > > > > > > > Himanshu Chauhan (5): > > > > riscv: Introduce support for hardware break/watchpoints > > > > riscv: Add breakpoint and watchpoint test for riscv > > > > riscv: ptrace support for hardware break/watchpoints > > > > selftests/breakpoints: extend riscv test for ptrace hw > > > > break/watchpoints > > > > MAINTAINERS: Add entry for RISC-V Debugging > > > > > > > > MAINTAINERS | 9 + > > > > arch/riscv/Kconfig | 2 + > > > > arch/riscv/include/asm/hw_breakpoint.h | 299 +++++++ > > > > arch/riscv/include/asm/kdebug.h | 3 +- > > > > arch/riscv/include/asm/processor.h | 18 + > > > > arch/riscv/include/uapi/asm/ptrace.h | 53 ++ > > > > arch/riscv/kernel/Makefile | 1 + > > > > arch/riscv/kernel/hw_breakpoint.c | 677 ++++++++++++++++ > > > > arch/riscv/kernel/process.c | 5 + > > > > arch/riscv/kernel/ptrace.c | 507 ++++++++++++ > > > > arch/riscv/kernel/traps.c | 6 + > > > > include/uapi/linux/elf.h | 4 + > > > > tools/include/uapi/linux/elf.h | 2 + > > > > tools/testing/selftests/breakpoints/Makefile | 5 + > > > > .../breakpoints/breakpoint_test_riscv.c | 765 ++++++++++++++++++ > > > > 15 files changed, 2355 insertions(+), 1 deletion(-) > > > > create mode 100644 arch/riscv/include/asm/hw_breakpoint.h > > > > create mode 100644 arch/riscv/kernel/hw_breakpoint.c > > > > create mode 100644 tools/testing/selftests/breakpoints/breakpoint_test_riscv.c > > > > > > > > -- > > > > 2.43.0 > > > > > > > > > > > > > _______________________________________________ > > > linux-riscv mailing list > > > linux-riscv@lists.infradead.org > > > http://lists.infradead.org/mailman/listinfo/linux-riscv
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