Commit 3e360ef0c0a1f ("kselftest/arm64: Corrupt P0 in the irritator when
testing SSVE") added corruption of P0 to the sve-test case in order to
ensure that the predicate registers were covered as part of the
corruption.  On SME only systems this results in an illegal instruction
since signal handlers are run out of streaming mode and the predicate
registers do not exist out of streaming mode without SVE.  Switch to
entering and exiting streaming mode in the irritator, this will reset
all relevant registers to 0 if they somehow weren't already by the
signal entry.

Fixes: 3e360ef0c0a1f ("kselftest/arm64: Corrupt P0 in the irritator when testing SSVE")
Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 tools/testing/selftests/arm64/fp/sve-test.S | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/tools/testing/selftests/arm64/fp/sve-test.S b/tools/testing/selftests/arm64/fp/sve-test.S
index 80e072f221cd..7ef7835389e7 100644
--- a/tools/testing/selftests/arm64/fp/sve-test.S
+++ b/tools/testing/selftests/arm64/fp/sve-test.S
@@ -298,15 +298,20 @@ function irritator_handler
 	add	x0, x0, #1
 	str	x0, [x2, #ucontext_regs + 8 * 23]
 
+#ifndef SSVE
 	// Corrupt some random Z-regs
 	movi	v0.8b, #1
 	movi	v9.16b, #2
 	movi	v31.8b, #3
 	// And P0
 	ptrue	p0.d
-#ifndef SSVE
 	// And FFR
 	wrffr	p15.b
+#else
+	// Enter and exit streaming mode, will reset all of the V, Z, P
+	// and FFR registers that the system has.
+	smstart_sm
+	smstop
 #endif
 
 	ret

---
base-commit: f5098b6bae761e346ebcd9da7f95622c04733cff
change-id: 20260731-arm64-sve-test-sme-only-464e409dcffa

Best regards,
--  
Mark Brown <broonie@kernel.org>

On Fri, 31 Jul 2026 21:50:52 +0100, Mark Brown wrote:
> Commit 3e360ef0c0a1f ("kselftest/arm64: Corrupt P0 in the irritator when
> testing SSVE") added corruption of P0 to the sve-test case in order to
> ensure that the predicate registers were covered as part of the
> corruption.  On SME only systems this results in an illegal instruction
> since signal handlers are run out of streaming mode and the predicate
> registers do not exist out of streaming mode without SVE.  Switch to
> entering and exiting streaming mode in the irritator, this will reset
> all relevant registers to 0 if they somehow weren't already by the
> signal entry.
> 
> [...]

Applied to arm64 (for-next/selftests), thanks!

[1/1] kselftest/arm64: Don't write to P0 in irritator on SME only systems
      https://git.kernel.org/arm64/c/2b989c411ab9

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev