From: Surendra Singh Chouhan <kr494167@gmail.com>
cs42xx8_spi_probe() configures reg_bits=16 so regmap sends a 2-byte
address field over SPI big-endian. The SPI frame format requires the
chip address byte (0x9E for write, 0x9F for read) to be in the high
byte of the 16-bit address field and the register address in the low
byte:
write: [0x9E, MAP_addr, data]
read: [0x9F, MAP_addr] -> [data]
However, write_flag_mask was set to 0x9E and read_flag_mask to 0x9F.
Because 0x9E is a 16-bit value of 0x009E, regmap OR'd 0x9E into the
low byte (bits 7..0) of the address instead of the high byte (bits
15..8), corrupting the register address on the wire.
Fix this by setting write_flag_mask to 0x9E00 and read_flag_mask to
0x9F00.
Fixes: 3158f585f4f2 ("ASoC: cs42xx8: Add SPI bus support for CS42448/CS42888 codec")
Signed-off-by: Surendra Singh Chouhan <kr494167@gmail.com>
---
sound/soc/codecs/cs42xx8-spi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/soc/codecs/cs42xx8-spi.c b/sound/soc/codecs/cs42xx8-spi.c
index 2e4b8e6c4081..cf5e39a44f94 100644
--- a/sound/soc/codecs/cs42xx8-spi.c
+++ b/sound/soc/codecs/cs42xx8-spi.c
@@ -52,8 +52,8 @@ static int cs42xx8_spi_probe(struct spi_device *spi)
* write_flag_mask/read_flag_mask are OR'd into that address field:
*/
config.reg_bits = 16;
- config.write_flag_mask = 0x9E;
- config.read_flag_mask = 0x9F;
+ config.write_flag_mask = 0x9E00;
+ config.read_flag_mask = 0x9F00;
ret = cs42xx8_probe(&spi->dev,
devm_regmap_init_spi(spi, &config), drvdata);
--
2.55.0