This series adds support for the Audio Core Clock Controller (AUDIOCORECC)
and Audio Core CSR resets on Qualcomm Shikra SoC. The Audio Core Clocks and
Resets support differs across Shikra variants based on Audio subsystem
enablement as follows:
- CQM variant: The QAIF driver runs on HLOS, hence both clocks and resets
are required to be supported on HLOS.
- CQS variant: The QAIF driver runs on the Modem, and required clocks are
handled on Modem, so from HLOS only resets are needed.
- IQS variant: no soundwire codes, hence no clocks/resets are needed.
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
Changes in v4:
- Dropped "clk: qcom: common: Register reset controller only when resets are present" patch
- Sashiko AI review pointed a valid GDSC-only corner case issue with this
change, will address it in a separate patch.
- This patch is not needed for this series, after splitting AudioCoreCC
clocks and resets into different devices.
- Added NULL check for device_get_match_data() in driver [Sashiko AI review]
- Removed unnecessary <linux/mod_devicetable.h> include in driver [Uwe]
- Collected the R-By tags received on v2.
- Link to v3: https://lore.kernel.org/r/20260723-shikra-audiocorecc-v3-0-90b878ae0d4e@oss.qualcomm.com
Changes in v3:
- Rebased on next-20260722, as the dependent RPMCC/GCC and Shikra base
DTS changes were merged.
- Separated the audiocorecc and audiocore_csr bindings into separate schema
docs [Rob]
- Moved the AudioCoreCSR schema to bindings/reset/, since it now only
describes a reset controller.
- Updated audiocorecc DTS node to use status reserved [Konrad]
- Kept audiocore_csr node globally enabled by default in DTS [Konrad]
- Collected all the R-By received on v1.
- Link to v2: https://lore.kernel.org/r/20260708-shikra-audiocorecc-v2-0-b320d822cdd0@oss.qualcomm.com
Changes in v2:
- Separated AudioCoreCC and AudioCoreCSR nodes as both resides in two
different register spaces. [Konrad]
- Updated bindings and driver patches to handle the separate node
compatibles.
- Updated resets in driver patch to handle HW_CTL bit.
- Link to v1: https://lore.kernel.org/r/20260605-shikra-audiocorecc-v1-0-7ee6b5f2d928@oss.qualcomm.com
---
Imran Shaik (3):
dt-bindings: clock: qcom: Add Qualcomm Shikra AudioCoreCC and AudioCoreCSR
clk: qcom: Add Audio Core clock controller support on Qualcomm Shikra SoC
arm64: dts: qcom: shikra: Add support for AudioCoreCC and AudioCoreCSR nodes
.../bindings/clock/qcom,shikra-audiocorecc.yaml | 55 ++
.../bindings/reset/qcom,shikra-audiocore-csr.yaml | 42 ++
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 4 +
arch/arm64/boot/dts/qcom/shikra.dtsi | 17 +
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/audiocorecc-shikra.c | 810 +++++++++++++++++++++
.../dt-bindings/clock/qcom,shikra-audiocorecc.h | 49 ++
8 files changed, 988 insertions(+)
---
base-commit: b4515cf4156356e8f4fe6e0fdc17f59adab9772f
change-id: 20260605-shikra-audiocorecc-85efef073474
Best regards,
--
Imran Shaik <imran.shaik@oss.qualcomm.com>