The XGMAC DMA_MODE register has an INTM field (bits 13:12) that
controls interrupt routing behavior for DMA transfer completion
events:

  00 (default): sbd_perch_* are pulse signals, sbd_intr_o is also
                asserted for each completion event.
  01:          sbd_perch_* are level signals, sbd_intr_o is NOT
                asserted for packet transfer completion events.

When multi-MSI is enabled (dma_cfg->multi_msi_en), per-channel TX/RX
interrupts are expected to arrive on their dedicated lines
(sbd_perch_tx_intr_o / sbd_perch_rx_intr_o).  In the default INTM=00
mode, sbd_intr_o also fires for DMA completion events, but the
multi-MSI handler stmmac_mac_interrupt() only processes MAC-layer
events (LPI, PMT, timestamps) and does not service DMA channels,
silently dropping the interrupt.

Set INTM to mode 1 when multi-MSI is enabled, following the same
pattern as the GMAC4 DMA_BUS_MODE_INTM configuration in commit
6ccf12ae111e ("net: stmmac: use interrupt mode INTM=1 for multi-MSI").

Signed-off-by: Zxyan Zhu <zxyan0222@gmail.com>
---
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h     | 2 ++
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 9 +++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index 61b6d45a02f5..f8ab347f7b5b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
@@ -320,6 +320,8 @@
 /* DMA Registers */
 #define XGMAC_DMA_MODE			0x00003000
 #define XGMAC_SWR			BIT(0)
+#define XGMAC_INTM_MASK			GENMASK(13, 12)
+#define XGMAC_INTM_MODE1		0x1
 #define XGMAC_DMA_SYSBUS_MODE		0x00003004
 #define XGMAC_WR_OSR_LMT		GENMASK(29, 24)
 #define XGMAC_RD_OSR_LMT		GENMASK(21, 16)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
index 03437f1cf3df..72aceb06f5af 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
@@ -31,6 +31,15 @@ static void dwxgmac2_dma_init(void __iomem *ioaddr,
 		value |= XGMAC_EAME;
 
 	writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
+
+	/*
+	 * Route DMA interrupts to per-channel lines when multi-MSI enabled.
+	 */
+	if (dma_cfg->multi_msi_en) {
+		value = readl(ioaddr + XGMAC_DMA_MODE);
+		value = u32_replace_bits(value, XGMAC_INTM_MODE1, XGMAC_INTM_MASK);
+		writel(value, ioaddr + XGMAC_DMA_MODE);
+	}
 }
 
 static void dwxgmac2_dma_init_chan(struct stmmac_priv *priv,

base-commit: 1df10cef2d1e7f9f2fb7eddb67fc70d3abf101f9
-- 
2.34.1

Hi,

On 7/23/26 15:24, Zxyan Zhu wrote:
> The XGMAC DMA_MODE register has an INTM field (bits 13:12) that
> controls interrupt routing behavior for DMA transfer completion
> events:
> 
>   00 (default): sbd_perch_* are pulse signals, sbd_intr_o is also
>                 asserted for each completion event.
>   01:          sbd_perch_* are level signals, sbd_intr_o is NOT
>                 asserted for packet transfer completion events.
> 
> When multi-MSI is enabled (dma_cfg->multi_msi_en), per-channel TX/RX
> interrupts are expected to arrive on their dedicated lines
> (sbd_perch_tx_intr_o / sbd_perch_rx_intr_o).  In the default INTM=00
> mode, sbd_intr_o also fires for DMA completion events, but the
> multi-MSI handler stmmac_mac_interrupt() only processes MAC-layer
> events (LPI, PMT, timestamps) and does not service DMA channels,
> silently dropping the interrupt.
> 
> Set INTM to mode 1 when multi-MSI is enabled, following the same
> pattern as the GMAC4 DMA_BUS_MODE_INTM configuration in commit
> 6ccf12ae111e ("net: stmmac: use interrupt mode INTM=1 for multi-MSI").
> 
> Signed-off-by: Zxyan Zhu <zxyan0222@gmail.com>

Same logic as in dwmac4, this looks good to me,

Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>

Maxime