[Patch v3 0/8] perf/x86: Miscellaneous PMU bug fixes and optimizations

Dapeng Mi posted 8 patches 1 week ago
arch/x86/events/core.c       |  45 ++++++++++++----
arch/x86/events/intel/core.c | 101 ++++++++++++++++++++++++++---------
arch/x86/events/intel/ds.c   |   7 ---
arch/x86/events/perf_event.h |  12 ++---
4 files changed, 113 insertions(+), 52 deletions(-)
[Patch v3 0/8] perf/x86: Miscellaneous PMU bug fixes and optimizations
Posted by Dapeng Mi 1 week ago
Changes since v2:
- Patch 6/8: Fix the typo in comments (Thomas).
- Patch 8/8: New patch which prevents drain_pebs() reentry.

Changes since v1:
- Patch 3/7: Ensure cpuc->pmu is not the static pmu before calling
  hybrid_pmu(cpuc->pmu) in intel_pmu_cpu_dead() (Sashiko).

This series fixes recently found x86 core PMU bugs. Most of bugs are
found by Sashiko in reviewing the "Support SIMD/eGPRs/SSP registers 
sampling for perf" patch-set, e.g.,
https://lore.kernel.org/all/20260706022123.480411F000E9@smtp.kernel.org/
https://lore.kernel.org/all/20260706021852.DE2ED1F000E9@smtp.kernel.org/

The patch 7/8 optimizes ACR handling in match_prev_assignment() and
mitigate the performance overhead.

The patch 8/8 enhances intel_pmu_drain_pebs_buffer() to prevent
drain_pebs() reentry.

Tests:
Below test cases are run on Diamonds and Novalake. No issues are found.
- Perf stat test
  $ perf test 119
- Perf record tests 
  $ perf test 155
- Perf record LBR tests
  $ perf test 156

History:
v2: https://lore.kernel.org/all/20260713082734.3162099-1-dapeng1.mi@linux.intel.com/ 
v1: https://lore.kernel.org/all/20260710065128.1799838-1-dapeng1.mi@linux.intel.com/

Dapeng Mi (8):
  perf/x86: Unregister PMI handler on PMU init failure
  perf/x86: Free hybrid state on PMU init failure
  perf/x86: Guard intel_pmu_cpu_dead() against invalid hybrid PMU casts
  perf/x86/intel: Unwind cpuc state if PEBS buffer setup fails
  perf/x86: Remove stale fixed counter helper and fix hybrid PMU access
  perf/x86/intel: Fix intel_cap handling on hybrid PMUs
  perf/x86: Optimize ACR handling in match_prev_assignment()
  perf/x86/intel: Prevent drain_pebs() reentry

 arch/x86/events/core.c       |  45 ++++++++++++----
 arch/x86/events/intel/core.c | 101 ++++++++++++++++++++++++++---------
 arch/x86/events/intel/ds.c   |   7 ---
 arch/x86/events/perf_event.h |  12 ++---
 4 files changed, 113 insertions(+), 52 deletions(-)


base-commit: edda9051e267b7390c7ce24b1b71434414ad156e
-- 
2.34.1
Re: [Patch v3 0/8] perf/x86: Miscellaneous PMU bug fixes and optimizations
Posted by Chen, Zide 3 days, 14 hours ago
For the whole series:
Reviewed-by: Zide Chen <zide.chen@intel.com>


On 7/17/2026 3:03 AM, Dapeng Mi wrote:
> Changes since v2:
> - Patch 6/8: Fix the typo in comments (Thomas).
> - Patch 8/8: New patch which prevents drain_pebs() reentry.
> 
> Changes since v1:
> - Patch 3/7: Ensure cpuc->pmu is not the static pmu before calling
>   hybrid_pmu(cpuc->pmu) in intel_pmu_cpu_dead() (Sashiko).
> 
> This series fixes recently found x86 core PMU bugs. Most of bugs are
> found by Sashiko in reviewing the "Support SIMD/eGPRs/SSP registers 
> sampling for perf" patch-set, e.g.,
> https://lore.kernel.org/all/20260706022123.480411F000E9@smtp.kernel.org/
> https://lore.kernel.org/all/20260706021852.DE2ED1F000E9@smtp.kernel.org/
> 
> The patch 7/8 optimizes ACR handling in match_prev_assignment() and
> mitigate the performance overhead.
> 
> The patch 8/8 enhances intel_pmu_drain_pebs_buffer() to prevent
> drain_pebs() reentry.
> 
> Tests:
> Below test cases are run on Diamonds and Novalake. No issues are found.
> - Perf stat test
>   $ perf test 119
> - Perf record tests 
>   $ perf test 155
> - Perf record LBR tests
>   $ perf test 156
> 
> History:
> v2: https://lore.kernel.org/all/20260713082734.3162099-1-dapeng1.mi@linux.intel.com/ 
> v1: https://lore.kernel.org/all/20260710065128.1799838-1-dapeng1.mi@linux.intel.com/
> 
> Dapeng Mi (8):
>   perf/x86: Unregister PMI handler on PMU init failure
>   perf/x86: Free hybrid state on PMU init failure
>   perf/x86: Guard intel_pmu_cpu_dead() against invalid hybrid PMU casts
>   perf/x86/intel: Unwind cpuc state if PEBS buffer setup fails
>   perf/x86: Remove stale fixed counter helper and fix hybrid PMU access
>   perf/x86/intel: Fix intel_cap handling on hybrid PMUs
>   perf/x86: Optimize ACR handling in match_prev_assignment()
>   perf/x86/intel: Prevent drain_pebs() reentry
> 
>  arch/x86/events/core.c       |  45 ++++++++++++----
>  arch/x86/events/intel/core.c | 101 ++++++++++++++++++++++++++---------
>  arch/x86/events/intel/ds.c   |   7 ---
>  arch/x86/events/perf_event.h |  12 ++---
>  4 files changed, 113 insertions(+), 52 deletions(-)
> 
> 
> base-commit: edda9051e267b7390c7ce24b1b71434414ad156e