This series implements support for the RISC-V IOMMU hardware performance
monitor.

The RISC-V IOMMU PMU driver is implemented as an auxiliary device driver
created by the parent RISC-V IOMMU driver. Therefore, the child driver
can obtain resources and information from the parent device, such as
the MMIO base address and IRQ number.

Changed in v3:
- Rebased oto v7.2-rc3
- Use hi_lo_writeq/readq to access register
- Pick comments from sashiko-bot as follows
- Set IRQ CPU affinity
- Remove IRQF_ONESHOT flag when request irq
- Adjust cycle event check by checking event_id field only
- Fix bug for group events verificaiton
- Fix KASAN issue about casting 32-bit variable to unsigned long pointer
- Clear IPSR pending bit before starting counter
- Clear OF bit in event selector register in irq handler
- Release irq by devm instead of explicit free_irq

Changed in v2:
- Rebased onto v7.2-rc1
- Use hi-lo-hi mechanism to read counter.
  Suggested by Guo Ren and David Laight

Changed in v1:
- Rebased onto v6.19-rc8
- Pick all suggestions and feedbacks from v1 series
- Add cpu hotplug implementation to avoid race enablement
- Move PMU-related definition from header to c file
- Change PMU driver to auxiliary device driver

Changed in RFC:
- Rebase onto v6.13-rc7
- Clear interrupt pending before handling interrupt
- Fix the counter value issue caused by OF bit in the cycle counter.
- Invoke riscv_iommu_hpm_disable() instead of riscv_iommu_pmu_uninit()
  in riscv_iommu_remove()

Zong Li (2):
  drivers/perf: riscv-iommu: add risc-v iommu pmu driver
  iommu/riscv: create a auxiliary device for HPM

 drivers/iommu/riscv/Kconfig      |   1 +
 drivers/iommu/riscv/iommu-bits.h |  61 ---
 drivers/iommu/riscv/iommu.c      |  19 +
 drivers/perf/Kconfig             |  12 +
 drivers/perf/Makefile            |   1 +
 drivers/perf/riscv_iommu_pmu.c   | 722 +++++++++++++++++++++++++++++++
 6 files changed, 755 insertions(+), 61 deletions(-)
 create mode 100644 drivers/perf/riscv_iommu_pmu.c

-- 
2.43.7

>This series implements support for the RISC-V IOMMU hardware performance
>monitor.
>
>The RISC-V IOMMU PMU driver is implemented as an auxiliary device driver
>created by the parent RISC-V IOMMU driver. Therefore, the child driver
>can obtain resources and information from the parent device, such as
>the MMIO base address and IRQ number.
>

Hi Zong,

I tested this series on a riscv64 QEMU with a QEMU NVMe device.
The NVMe device was enumerated correctly, and the RISC-V IOMMU PMU
events could be counted successfully while running I/O to the NVMe disk.

The following command completed successfully:

  perf stat -a \
    -e riscv_iommu_pmu_3010000.iommu/tlb_miss/ \
    -e riscv_iommu_pmu_3010000.iommu/cycle/ \
    -e riscv_iommu_pmu_3010000.iommu/untranslated_req/ \
    -e riscv_iommu_pmu_3010000.iommu/s_vs_pt_walks/ \
    dd if=/dev/nvme0n1 of=/dev/null bs=1M count=100

100+0 records in
100+0 records out
104857600 bytes (105 MB, 100 MiB) copied, 1.43612 s, 73.0 MB/s

 Performance counter stats for 'system wide':

             26449      riscv_iommu_pmu_3010000.iommu/tlb_miss/                                      
            256659      riscv_iommu_pmu_3010000.iommu/cycle/                                      
             32063      riscv_iommu_pmu_3010000.iommu/untranslated_req/                                      
            132245      riscv_iommu_pmu_3010000.iommu/s_vs_pt_walks/                                      

       1.464510700 seconds time elapsed

Tested-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>

On Tue, Jul 14, 2026 at 01:36:20AM -0700, Zong Li wrote:
> This series implements support for the RISC-V IOMMU hardware performance
> monitor.
>
> The RISC-V IOMMU PMU driver is implemented as an auxiliary device driver
> created by the parent RISC-V IOMMU driver. Therefore, the child driver
> can obtain resources and information from the parent device, such as
> the MMIO base address and IRQ number.

I tested this series on QEMU and it works as expected.

Test setup:
 - Base: v7.2-rc2, both patches applied cleanly.
 - Kernel: rv64 defconfig with CONFIG_RISCV_IOMMU=y, CONFIG_RISCV_IOMMU_PCI=y,
   CONFIG_RISCV_IOMMU_PMU=y and CONFIG_PERF_EVENTS=y.
 - QEMU 10.2.0: -M virt,aia=aplic-imsic -device riscv-iommu-pci
   (hpm-counters=31).

Results:
 - The RISC-V IOMMU probes, the auxiliary device is created and the PMU
   driver registers successfully:
     riscv_iommu_pmu ...: Registered with 32 counters
 - The PMU shows up under
   /sys/bus/event_source/devices/riscv_iommu_pmu_<BDF> with the expected
   9 events (cycle, untranslated_req, translated_req, ats_trans_req,
   tlb_miss, dd_walk, pd_walk, s_vs_pt_walks, g_pt_walks) and 7 format
   attributes; "perf list" enumerates all of them.
 - No oops/WARN/KASAN splat during boot or driver bring-up.

Tested-by: Chen Pei <cp0613@linux.alibaba.com>

Thanks,
Pei