An issue has been reported that xHCI host controller doesn't come back
from resume on some systems.  This issue has a failure rate, but that
failure rate is confusingly tied to the size of the VRAM reservation
that the BIOS makes.

That is if the VRAM reservation is small (for example 512MB) then no
failures. There are some comments that mention that the larger the VRAM
size the higher the failure rate.  I personally don't really understand
why this would matter, but I would like to mention it in case it jogs
anyone else's brain.

Various workarounds work:
 * Using legacy interrupts instead of MSI
 * Resetting controller on resume
 * Creating device link dependency between XHCI and display PCI devices
   (for device resume ordering)

None of those workarounds appear to get at the root of the problem to me
though.

I did some tracing around the code and cross referenced the PCI spec.
The XHCI controller should be in D3cold during suspend and thus should go
through a D3->D0 transition.  The PCI spec says that D3 transitions need
10ms delay.

However we don't have any mandatory delays for endpoints in D3cold, only
bridges have this.  For endpoints we only have mandatory delays in D3hot.

So my suspicion is that adding a mandatory delay for the D3cold to D0
transition will help this issue, which is what this patch series does.

Cc: mrh@frame.work
Cc: stern@rowland.harvard.edu
Cc: hannes@vonhaugwitz.com
Cc: jase_harley@protonmail.com
Cc: superveridical@gmail.com
Cc: david.c.hubbard@gmail.com
Cc: bugzilla@logical.ink
Cc: michal.pecio@gmail.com

Mario Limonciello (1):
  PCI: Apply mandatory recovery delay on return from D3cold

 drivers/pci/pci.c | 26 ++++++++++++++++++++------
 1 file changed, 20 insertions(+), 6 deletions(-)

-- 
2.43.0