This series builds on Andrew Jones's earlier RFC [1]. It lets userspace
check for RVA23U64 conformance in one call, instead of walking hwprobe +
prctl across every mandatory extension.
The series adds a small framework that resolves profile-class bases (IMA
and RVA23U64) from the kernel's ISA extension bitmap at init time, and
surfaces the result through both /proc/cpuinfo and hwprobe. Later patches
can add RVA23S64, and backward RVA22 / RVA20 detection, to
riscv_set_isa_bases() without changes to the surrounding code.
Series outline (v4):
Housekeeping, clean-ups:
1. dt-bindings: sort the multi-letter Z extensions alphanumerically.
2. hwprobe.rst: normalize indentation.
3. hwprobe.rst: document EXT_ZICFISS / EXT_ZICFILP.
4. Standardize the single-letter extension macros to uppercase
(RISCV_ISA_EXT_a -> RISCV_ISA_EXT_A, etc.).
Per-extension cpufeature parsing + hwprobe export:
5. Zicclsm.
6. Ziccamoa, Ziccif, Ziccrse, Za64rs.
7. B (the Zba/Zbb/Zbs set).
Zic64b (new first-class extension):
8. dt-binding, with a schema check.
9. cpufeature parsing + hwprobe export.
10-12. dts: declare zic64b in the SpacemiT K3, SpacemiT K1, and Sophgo
SG2044 device trees.
RVA23U64 base detection and exposure:
13. riscv_have_user_pmlen(): accessor for user pointer-masking PMLEN
support.
14. cpufeature: per-hart and host-wide isa_bases bitmaps; IMA and
RVA23U64 detection lives here.
15. /proc/cpuinfo: print "isa bases:" and "hart isa bases:", e.g.
rva23u64.
16. hwprobe: expose RVA23U64.
Tested on both K3 Pico ITX and QEMU with -cpu rva23s64,sv39=on:
- /proc/cpuinfo reports "isa bases : rv64ima rva23u64" on both the
aggregated and per-hart lines.
- hwprobe RISCV_HWPROBE_KEY_BASE_BEHAVIOR returns
BASE_BEHAVIOR_IMA | BASE_BEHAVIOR_RVA23U64.
Based on v7.1-rc6 plus [2]; happy to rebase onto another tree if needed.
A branch is available for all patches in the series: [3].
Note: [2] is only required to save the merge effort for adding 'Zic64b'
and 'Ziccrse' into the same k3.dtsi file.
Link: Andrew's RFC v1:
https://lore.kernel.org/linux-riscv/20260206002349.96740-1-andrew.jones@oss.qualcomm.com/ [1]
Link: Prerequisite for applying on K3 w/Ziccrse:
https://lore.kernel.org/all/20260602070257-KYC5031219@kernel.org/ [2]
Link: Branch: https://github.com/docularxu/linux/commits/b4/rva23u64-hwprobe-v4/ [3]
Changes in v4:
- New patch: sort the multi-letter Z extensions alphanumerically in the
dt-binding (Conor), and place zic64b at its sorted position.
- Zic64b cpufeature: validate only the CBO block sizes that are present;
overlaps Qingwei Hu's earlier patch, so it is now authored by Qingwei.
- Document EXT_ZICFISS / EXT_ZICFILP: cite the riscv-cfi v1.0 tag commit.
- Picked up Inochi Amaoto's Acked-by (SG2044 dts) and Andrew Jones's
Reviewed-by (documentation patch).
- Link to v3: https://patch.msgid.link/20260603-rva23u64-hwprobe-v2-v3-0-5529a7b28384@gmail.com
Changes in v3:
- Add Zic64b as a first-class ISA extension: dt-binding, cpufeature
parsing with a validate check, hwprobe export, and device-tree
declarations for K3/K1/SG2044.
- Patch 1 is now a clean up of hwprobe.rst indentation.
- Document RISCV_HWPROBE_EXT_ZICFILP alongside ZICFISS.
- Move the Zicclsm hwprobe.rst entry to the IMA_EXT_1 section to match
its bit allocation.
- Collect Anup Patel's Acked-by/Reviewed-by on Patch 3, the capitalization.
- In cpufeature.c, set the local ext_mask with __set_bit().
- Update Guodong Xu's email to docular.xu@gmail.com.
- Link to v2: https://patch.msgid.link/20260511-rva23u64-hwprobe-v2-v2-0-21c5a544f1dc@riscstar.com
Changes in v2 (since Andrew's RFC v1):
- Rebased onto v7.1-rc2.
- Reworked rva23u64 detection into per-hart and host isa_bases bitmaps,
shared by /proc/cpuinfo and hwprobe.
- Scoped to IMA and RVA23U64 (RVA23S64, RVA20/RVA22 cpuinfo output deferred).
- Link to v1: https://lore.kernel.org/linux-riscv/20260206002349.96740-1-andrew.jones@oss.qualcomm.com
Signed-off-by: Guodong Xu <docular.xu@gmail.com>
---
Andrew Jones (4):
riscv: hwprobe.rst: Make indentation consistent
riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to cpufeature and hwprobe
riscv: Add B to hwcap and hwprobe
riscv: Add a getter for user PMLEN support
Charlie Jenkins (1):
riscv: Standardize extension capitalization
Guodong Xu (9):
dt-bindings: riscv: sort multi-letter Z extensions alphanumerically
riscv: hwprobe.rst: Document EXT_ZICFISS and EXT_ZICFILP
dt-bindings: riscv: Add Zic64b extension description
riscv: dts: spacemit: k3: Add Zic64b ISA extension
riscv: dts: spacemit: k1: Add Zic64b ISA extension
riscv: dts: sophgo: sg2044: Add Zic64b ISA extension
riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection
riscv: cpu: Output isa bases lines in cpuinfo
riscv: hwprobe: Introduce rva23u64 base behavior
Jesse Taube (1):
riscv: Add Zicclsm to cpufeature and hwprobe
Qingwei Hu (1):
riscv: Add Zic64b to cpufeature and hwprobe
Documentation/arch/riscv/hwprobe.rst | 240 ++++++++++++---------
.../devicetree/bindings/riscv/extensions.yaml | 204 ++++++++++--------
arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 128 +++++------
arch/riscv/boot/dts/spacemit/k1.dtsi | 80 +++----
arch/riscv/boot/dts/spacemit/k3.dtsi | 48 ++---
arch/riscv/include/asm/cpufeature.h | 14 ++
arch/riscv/include/asm/hwcap.h | 24 ++-
arch/riscv/include/asm/processor.h | 4 +
arch/riscv/include/asm/switch_to.h | 4 +-
arch/riscv/include/uapi/asm/hwcap.h | 1 +
arch/riscv/include/uapi/asm/hwprobe.h | 10 +-
arch/riscv/kernel/cpu.c | 26 +++
arch/riscv/kernel/cpufeature.c | 183 ++++++++++++++--
arch/riscv/kernel/process.c | 12 ++
arch/riscv/kernel/sys_hwprobe.c | 34 ++-
arch/riscv/kvm/isa.c | 16 +-
arch/riscv/kvm/main.c | 2 +-
arch/riscv/kvm/vcpu_fp.c | 20 +-
arch/riscv/kvm/vcpu_onereg.c | 6 +-
arch/riscv/kvm/vcpu_vector.c | 10 +-
tools/testing/selftests/riscv/hwprobe/which-cpus.c | 2 +-
21 files changed, 680 insertions(+), 388 deletions(-)
---
base-commit: 99c201dabc35bbd21252c4c682488209dcb4295e
change-id: 20260508-rva23u64-hwprobe-v2-1d20739cbb8e
Best regards,
--
Guodong Xu <docular.xu@gmail.com>