This series introduces the Qualcomm Audio Interface (QAIF) driver for
the Shikra audio platform.
Hardware IP Overview
====================
QAIF (Qualcomm Audio Interface) is a fully configurable DMA-based audio
subsystem used to transmit and receive audio data over serial audio
interfaces (PCM, TDM, MI2S) and to provide a DMA interface for internal
codec connections. It manages two independent data paths:
Unified Audio Interface (AIF): Serialises and deserialises PCM audio
between system memory and external serial audio peripherals. Each
interface supports up to 8 independent data lanes, each configurable
as TX (speaker) or RX (mic). All lanes of an interface share a single
bit clock and frame sync. The AUD_INTFa hardware block controls the
serial protocol -- sync source (master/slave), sync mode (short/long
PCM, TDM, MI2S), sync delay and inversion, slot and sample widths,
active slot masks, lane enable/direction, mono/stereo mode and
full-cycle path support for long chip-to-chip connections.
Codec DMA Interface (CIF): Provides a parallel DMA interface to the
internal Bolero digital codec. The RDDMA path carries playback data
to Bolero and the WRDMA path carries capture data from Bolero. Each
channel has an INTF_CFG register controlling the active channel enable
mask, frame-sync selection, frame-sync delay, frame-sync output gating,
dynamic clock gating and 16-bit packing/unpacking.
DMA Engine: Read DMAs (RDDMA) fetch audio from DDR/TCM/LPM into a
shared on-chip SRAM latency buffer (SHRAM) and drain it to the
interface. Write DMAs (WRDMA) collect data from the interface into
SHRAM and write it to memory. Each DMA channel owns a private SHRAM
region. Two QSB master ports (QXM0 and QXM1) provide the memory
fabric. Burst sizes of 1/2/4/8/16 beats and up to 4 outstanding
transactions per DMA are supported.
Execution Environments (EE): Resources (DMAs, audio interfaces,
interface groups) are partitioned among up to 5 EEs via map registers.
Each EE receives an independent interrupt output. The interrupt
hierarchy has two levels: a summary register identifies the event class
(DMA period, underflow/overflow, error response, AUD_INTF
underflow/overflow, group done, rate detector, VFR), and per-resource
status registers identify the specific channel and event type.
Interface Grouping (Bonding): Multiple AIF and CIF interfaces can be
bonded into a group to start synchronously and align their DMA period
interrupts within half a frame duration using the RDDMA padding feature.
Rate Detector: Two rate detector blocks measure the frequency of
incoming frame sync or word select signals and generate interrupts on
rate change, undetected rate or sync timeout.
Block Diagram
=============
System Memory (DDR / LPM / TCM)
+---------------------------------+
| Circular Buffers (ping-pong) |
+----------+----------+-----------+
| ^
64-bit AXI 64-bit AXI
| |
+----------v----------+-----------+
| QSB Master Ports |
| +----------+ +----------+ |
| | QXM0 | | QXM1 | |
| +----+-----+ +-----+----+ |
+-------|--------------|----------+
| |
+-------v--------------v----------+
| Shared RAM (SHRAM) |
| +------------+ +------------+ |
| | QXM0 Read | | QXM0 Write | |
| | SHRAM | | SHRAM | |
| +------------+ +------------+ |
| +------------+ +------------+ |
| | QXM1 Read | | QXM1 Write | |
| | SHRAM | | SHRAM | |
| +------------+ +------------+ |
+---+--------+--------+-------+---+
| | | |
+---v--+ +--v---+ +--v---+ +-v----+
|RDDMA | |RDDMA | |WRDMA | |WRDMA |
| AIF | | CIF | | AIF | | CIF |
|[0..n]| |[0..n]| |[0..n]| |[0..n]|
+--+---+ +--+---+ +--+---+ +-+----+
| | ^ ^
| TX | TX | RX | RX
v v | |
+--+--------------------+ +----+----------+
| Unified Audio Intf | | Codec DMA |
| (AIF 0..12) | | Interface |
| | | (CIF) |
| AUD_INTFa block: | | |
| - Serializer (TX) | | RDDMA: DDR -> |
| - De-serializer (RX) | | internal |
| - Sync gen/detect | | codec |
| - Up to 8 data lanes | | WRDMA: codec |
| - PCM / TDM / MI2S | | -> DDR |
| - Near Pad Logic | | Up to 16 ch |
+--+--------------------+ +----+----------+
| Lane 0..7 (TX/RX) | Parallel bus
| Bit clk + Frame sync | + Frame sync
v v
+--+--------+ +------+------+
| External | | Internal |
| Serial | | Digital |
| Peripherals| | Codec |
| (PCM/TDM/ | | (Bolero/ |
| MI2S) | | WCD) |
+-----------+ +-------------+
Software Design
===============
The driver follows the standard ALSA SoC split:
qaif-cpu.c: CPU DAI component. Manages clocks, initialises regmap
bitfield handles for all DMA and interface control registers, implements
DAI ops (startup/shutdown/hw_free/hw_params/trigger) for both AIF and
CIF paths, registers an of_xlate_dai_name callback so that sound-dai
references using non-sequential DAI IDs resolve correctly, and parses
per-interface TDM/MI2S configuration from DT child nodes.
qaif-platform.c: PCM platform component. Handles DMA buffer allocation
(dma_alloc_pages()), PCM ops (open/close/hw_params/prepare/trigger/
pointer/mmap/copy), two-level IRQ dispatch with period-elapsed
notification, and component suspend/resume across power collapse.
qaif-shikra.c: Shikra SoC-specific variant descriptor. Provides all
register field definitions, DMA-to-DAI index maps, SHRAM geometry,
clock names and the DAI driver array. This abstraction keeps the core
driver portable across future QAIF integrations.
qaif.h / qaif-reg.h: Shared data structures, constants and the complete
MMIO register address map consumed by both the CPU and platform drivers.
common.c/h: This series also adds asoc_qcom_of_xlate_dai_name(), a shared
helper that resolves a sound-dai phandle argument to a DAI name by
searching the component DAI driver array by ID. Both lpass-cpu.c and
qaif-cpu.c use thin wrappers around this helper, replacing duplicate
private implementations.
The series is split by functionality to aid review -- register map and
data structures first, then CIF ops, AIF ops, probe infrastructure, PCM
ops, IRQ handling and finally the Shikra variant glue.
Tested on Shikra with 48 kHz stereo MI2S playback and capture over the
Audio Interface Zero (AIF0) and Bolero CDC DMA RX/TX paths.
Harendra Gautam (13):
dt-bindings: sound: Add Qualcomm QAIF DAI ID header
dt-bindings: sound: Add Qualcomm QAIF binding
MAINTAINERS: Add Qualcomm QAIF driver entry
ASoC: qcom: Add QAIF hardware register map
ASoC: qcom: Add QAIF shared data structures and variant interface
ASoC: qcom: Add QAIF CIF (CDC DMA) DAI ops
ASoC: qcom: Add QAIF AIF DAI ops
ASoC: qcom: Add generic of_xlate_dai_name helper to common
ASoC: qcom: lpass-cpu: Use asoc_qcom_of_xlate_dai_name helper
ASoC: qcom: Add QAIF regmap, DT parsing and platform init
ASoC: qcom: Add QAIF PCM operations
ASoC: qcom: Add QAIF IRQ handling, suspend/resume and platform register
ASoC: qcom: Add Shikra QAIF support
.../devicetree/bindings/sound/qcom,qaif.yaml | 361 ++++
MAINTAINERS | 10 +
include/dt-bindings/sound/qcom,qaif.h | 92 ++
sound/soc/qcom/Kconfig | 11 +
sound/soc/qcom/Makefile | 2 +
sound/soc/qcom/common.c | 34 +
sound/soc/qcom/common.h | 5 +
sound/soc/qcom/lpass-cpu.c | 19 +-
sound/soc/qcom/qaif-cpu.c | 1586 ++++++++++++++++++++
sound/soc/qcom/qaif-platform.c | 1169 +++++++++++++++
sound/soc/qcom/qaif-reg.h | 405 +++++
sound/soc/qcom/qaif-shikra.c | 585 ++++++++
sound/soc/qcom/qaif.h | 504 +++++++
13 files changed, 4769 insertions(+), 14 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/qcom,qaif.yaml
create mode 100644 include/dt-bindings/sound/qcom,qaif.h
create mode 100644 sound/soc/qcom/qaif-cpu.c
create mode 100644 sound/soc/qcom/qaif-platform.c
create mode 100644 sound/soc/qcom/qaif-reg.h
create mode 100644 sound/soc/qcom/qaif-shikra.c
create mode 100644 sound/soc/qcom/qaif.h
--
2.34.1