This series adds support for the Display clock controller (DISPCC) and
GPU Clock Controller (GPUCC) on Qualcomm Shikra SoC, by reusing the
respective QCM2290 SoC drivers.
As part of this, the series extends the QCM2290 GPUCC binding ABI to
include DSI1PHY and sleep clock inputs and updates the Agatti DT
accordingly to match new bindings.
Shikra GCC series link:
- https://lore.kernel.org/linux-clk/20260508-shikra-gcc-rpmcc-clks-v2-0-83238ba24060@oss.qualcomm.com/
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
Changes in v3:
- Updated the QCM2290 GCC patch to use the .clk_cbcr convention
- Extended the QCM2290 GPUCC bindings to add DSI1 PHY and Sleep clocks
- Separated the patches as per the review comments in v2 series
- Added Agatti DISPCC DT node changes as per the latest bindings changes
- Link to v2: https://lore.kernel.org/r/20260528-shikra-dispcc-gpucc-v2-0-953f246a0fbb@oss.qualcomm.com
Changes in v2:
- Dropped QCM2290 GCC critical clocks modelling to kept them ON from probe.
- Updated the QCM2290 DISPCC/GPUCC bindings to align for Shikra drivers reuse.
- Reused the QCM2290 DISPCC driver for Shikra without modernizing
(keeping the clock-names approach) for now to avoid potential bindings ABI breakage.
- Modernized QCM2290 GPUCC driver to use commmon qcom_cc_probe() model
and reuse for Shikra.
- Link to v1: https://lore.kernel.org/r/20260513-shikra-dispcc-gpucc-v1-0-5fd673146ab2@oss.qualcomm.com
---
Imran Shaik (12):
clk: qcom: gcc-qcm2290: Keep the critical clocks always-on from probe
dt-bindings: clock: qcom,qcm2290-dispcc: Add DSI1 PHY and sleep clocks
dt-bindings: clock: qcom: Add Qualcomm Shikra Display clock controller
dt-bindings: clock: qcom: Add Qualcomm Shikra GPU clock controller
clk: qcom: dispcc-qcm2290: Move to the latest common qcom_cc_probe() model
clk: qcom: dispcc-qcm2290: Switch to DT index based clk lookup
clk: qcom: dispcc-qcm2290: Update GDSC *wait_val values and flags
clk: qcom: gpucc-qcm2290: Move to the latest common qcom_cc_probe() model
clk: qcom: gpucc-qcm2290: Park RCG's clk source at XO during disable
clk: qcom: gpucc-qcm2290: Update GDSC *wait_val values and flags
clk: qcom: Add support for Qualcomm GPU Clock Controller on Shikra
arm64: dts: qcom: agatti: Add DSI1 PHY and sleep clocks to DISPCC node
.../bindings/clock/qcom,qcm2290-dispcc.yaml | 28 +++-
.../bindings/clock/qcom,qcm2290-gpucc.yaml | 4 +-
arch/arm64/boot/dts/qcom/agatti.dtsi | 10 +-
drivers/clk/qcom/dispcc-qcm2290.c | 87 ++++++-----
drivers/clk/qcom/gcc-qcm2290.c | 160 +++------------------
drivers/clk/qcom/gpucc-qcm2290.c | 117 ++++++---------
6 files changed, 149 insertions(+), 257 deletions(-)
---
base-commit: 9974969c14031a097d6b45bcb7a06bb4aa525c40
change-id: 20260513-shikra-dispcc-gpucc-6f59c23020f5
prerequisite-change-id: 20260429-shikra-gcc-rpmcc-clks-2094edfff3b0:v3
prerequisite-patch-id: 5a0fbdd458785da2d0e850c851a05046672ecadf
prerequisite-patch-id: 197da6bcb15cadc47869dba88c8020987b25c335
prerequisite-patch-id: a64476b2ba6e0f2a55928baf72ec32672ee0123c
prerequisite-patch-id: 63e4153eb0a47bb23d906be97cc4ce84f9821248
Best regards,
--
Imran Shaik <imran.shaik@oss.qualcomm.com>