From: Biju Das <biju.das.jz@bp.renesas.com>

Hi All,

This patch series aims to add audio support for the RZ/G3L SMARC EVK
platform using the SSIF-2 interface. PDM/SPDIF support is planned for a
later date.

SSI0 signals are connected to the DA7212 audio codec on the RZ/G3L SMARC
EVK. These signals are muxed with SD2 signals and are enabled through
the SYS.4 switch on the RZ/G3L SMARC SoM board. The audio clocks and MCK
are provided by the 5P35023B Versa Clock generator.

This patch series depend up on [1]
[1] https://lore.kernel.org/all/20260528070239.33352-1-biju.das.jz@bp.renesas.com/

v1->v2:
 * Dropped patch #1, #2, and #3 as they are accepted for renesas-devel for
   v7.2.
 * Updated commit description with clocks arranged in clock output index
   order.
 * Dropped assigning clock rates of the unused outputs (ref and diff2).
 * Added guard for snd_rzg3l with the SW_I3C_EN macro.
 * Sorted ssi0_pins.

Biju Das (2):
  arm64: dts: renesas: rzg3l-smarc-som: Enable versa clock generator
  arm64: dts: renesas: r9a08g046l48-smarc: Enable audio

 .../boot/dts/renesas/r9a08g046l48-smarc.dts   | 72 +++++++++++++++++++
 .../boot/dts/renesas/rzg3l-smarc-som.dtsi     | 40 +++++++++++
 2 files changed, 112 insertions(+)

-- 
2.43.0