Add device tree support and board enablement for audio on the
RZ/G3E SMARC EVK with a Dialog DA7212 codec.

This series includes:
  - CPG clock binding update for optional audio clock inputs
  - CPG driver support for RZ/G3E audio clocks and resets
  - Audio clock input nodes for RZ/V2H family DTSIs
  - R-Car Sound node for RZ/G3E SoC DTSI
  - Board-level enablement: I2C1, Versa3 clock generator, audio
    pinmux, and DA7212 codec on SMARC EVK

Audio configuration on SMARC EVK:
  - Codec: Dialog DA7212 on I2C1
  - Playback: SSI3
  - Capture: SSI4 -> SRC0 -> DVC0
  - MCLK: 12.288MHz from Versa3 clock generator
  - Format: I2S, R-Car Sound as clock master
  - SSI4 shares clock pins with SSI3 (shared-pin)

Changes:

v4:
 - Rebased onto a newer renesas-devel base (the CPG driver now
   already carries the DSI/LCDC module clocks and resets).
 - dt-bindings and clk driver: drop the AUDIO_CLKA input. AUDIO_CLKA
   is fed internally by the AUDIO_EXTAL pin, which the binding
   already describes, so adg_0_audio_clka is reparented on
   CLK_AUDIO_EXTAL (Geert Uytterhoeven).
 - clk driver: drop the internal core clocks Geert flagged as unused
   (pllcm33_div4_ddiv2, pllcm33_div4_ddiv2_div2, pllcln_div32,
   plldty_div2, plldty_div4, cdiv5_mainosc). pllcln_div4 is kept,
   since scu_0_clkx2 is parented on it.
 - clk driver: rename the audio module clocks and resets to the
   names Geert suggested (ssif_0_clk, scu_0_clk, scu_0_clkx2,
   dmacpp_0_clk, adg_0_clks1, adg_0_clk_195m, adg_0_audio_clk{a,b,c},
   ssiu_supply_clk; SCU_0_RESET_SRU, DMACpp_0_ARST,
   ADG_0_RST_RESET_ADG).
 - clk driver: the adg_ssi[0-9]_clk parent is left as CLK_PLLCLN_DIV8.
   Geert questioned this; the parent is unchanged, and the commit
   message now explains that the ADG muxes these outputs at runtime
   via ADG_AUDIO_CLK_SEL{0,1,2}.
 - dts sound node: rename the indexed clock-names and reset-names
   from the dotted form (ssi.N, src.N, adg.ssi.N, clk_a/b/c/i) to
   the hyphenated form (ssi-N, src-N, adg-ssi-N, audio-clka/b/c/i),
   and rename the sub-nodes from rcar_sound,xxx to the unprefixed
   ssi/ssiu/src/dvc/mix/ctu, matching the new RZ/G3E sound binding.
 - dts sound node: reorder the clocks and resets lists into
   ascending index order, annotate each phandle with a per-line
   comment, and drop the #sound-dai-cells / #clock-cells comment
   blocks.
 - dts: drop the audio_clka fixed-clock node from the RZ/V2H family
   DTSIs and from the pinctrl clocks/clock-names lists, consistent
   with dropping the AUDIO_CLKA input from the binding and driver.
 - Link to v3 at [2].

v3:
 - Splitout from v2 [1]
 - No code changes

v2:
 - Fix Rob's comment on  maxItems not needed with items lists.
 - Drop DMA ACK second cell from DT specifier

[1]: https://lore.kernel.org/all/20260402090524.9137-1-john.madieu.xa@bp.renesas.com/
[2]: https://lore.kernel.org/all/20260402163126.12135-1-john.madieu.xa@bp.renesas.com/

John Madieu (8):
  dt-bindings: clock: renesas: Add audio clock inputs for RZ/V2H family
  clk: renesas: r9a09g047: Add audio clock and reset support
  arm64: dts: renesas: rzv2h: Add audio clock inputs
  arm64: dts: renesas: r9a09g047: Add RZ/G3E Sound support
  arm64: dts: renesas: rzg3e-smarc-som: Add Versa3 clock generator
  arm64: dts: renesas: rzg3e-smarc-som: Add I2C1 support
  arm64: dts: renesas: rzg3e-smarc-som: add audio pinmux definitions
  arm64: dts: renesas: r9a09g047e57-smarc: add DA7212 audio codec
    support

 .../bindings/clock/renesas,rzv2h-cpg.yaml     |   6 +
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    | 496 +++++++++++++++++-
 .../boot/dts/renesas/r9a09g047e57-smarc.dts   | 114 ++++
 arch/arm64/boot/dts/renesas/r9a09g056.dtsi    |  20 +-
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi    |  20 +-
 .../boot/dts/renesas/rzg3e-smarc-som.dtsi     |  44 ++
 drivers/clk/renesas/r9a09g047-cpg.c           | 112 +++-
 7 files changed, 805 insertions(+), 7 deletions(-)

-- 
2.25.1