From: Nicholas Piggin <npiggin@gmail.com>

Extend the binding to cover details specific to the Tenstorrent RISC-V
IOMMU. In particular, a second register range is added which contains
M-privileged registers, e.g., PMAs and PMPs.

The RISC-V spec S-privileged registers remain in the first register
range and are compatible with "riscv,iommu" so the Linux driver does not
notice any difference, but the binding will be used by OpenSBI and
potentially other M-mode software.

Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joerg Roedel <joerg.roedel@amd.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[fustini: fix dt_binding_check errors]
Signed-off-by: Drew Fustini <fustini@kernel.org>
---
v2 changes:
- Fix dt_binding_check errors
- Add the Acked-by: from Joerg
- Drop RFC prefix

Link to v1:
https://lore.kernel.org/lkml/20260310003850.3837030-1-npiggin@gmail.com/

 .../bindings/iommu/riscv,iommu.yaml           | 62 ++++++++++++++++---
 1 file changed, 55 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
index d4838c3b3741..5aad8cf67840 100644
--- a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
@@ -32,22 +32,35 @@ properties:
   # should be specified along with 'reg' property providing MMIO location.
   compatible:
     oneOf:
-      - items:
+      - description: Platform (non-PCIe) IOMMU implementations
+        items:
           - enum:
               - qemu,riscv-iommu
           - const: riscv,iommu
-      - items:
+      - description: PCIe IOMMU implementations
+        items:
           - enum:
               - pci1efd,edf1
           - const: riscv,pci-iommu
+      - description: Tenstorrent IOMMUs implementing "riscv,iommu"
+        items:
+          - enum:
+              - tenstorrent,riscv-iommu
+          - const: riscv,iommu
 
   reg:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
     description:
-      For non-PCI devices this represents base address and size of for the
-      IOMMU memory mapped registers interface.
-      For PCI IOMMU hardware implementation this should represent an address
-      of the IOMMU, as defined in the PCI Bus Binding reference.
+      For non-PCI devices the first item represents base address and size of
+      for the IOMMU memory mapped registers interface.
+      For PCI IOMMU hardware implementation the first item should represent
+      an address of the IOMMU, as defined in the PCI Bus Binding reference.
+
+  reg-names:
+    items:
+      - const: base
+      - const: machine
 
   '#iommu-cells':
     const: 1
@@ -75,6 +88,31 @@ required:
 
 additionalProperties: false
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - tenstorrent,riscv-iommu
+    then:
+      properties:
+        reg:
+          items:
+            - description: IOMMU base registers
+            - description: Tenstorrent IOMMU machine mode registers.
+        reg-names:
+          items:
+            - const: base
+            - const: machine
+              description:
+                Region containing platform specific MMRs for machine-mode
+                configuration, such as PMA and PMP registers.
+    else:
+      properties:
+        reg:
+          maxItems: 1
+
 examples:
   - |+
     /* Example 1 (IOMMU device with wired interrupts) */
@@ -145,3 +183,13 @@ examples:
             };
         };
     };
+
+  - |+
+    /* Example 5 (Tenstorrent IOMMU device with MSIs) */
+    iommu5: iommu@d2020000 {
+        compatible = "tenstorrent,riscv-iommu", "riscv,iommu";
+        reg = <0xd2020000 0x10000 0xaa000000 0x10000>;
+        reg-names = "base", "machine";
+        msi-parent = <&imsics_smode>;
+        #iommu-cells = <1>;
+    };
-- 
2.43.0

On Tue, May 19, 2026 at 11:16:28PM -0700, Drew Fustini wrote:
> From: Nicholas Piggin <npiggin@gmail.com>
> 
> Extend the binding to cover details specific to the Tenstorrent RISC-V
> IOMMU. In particular, a second register range is added which contains
> M-privileged registers, e.g., PMAs and PMPs.
> 
> The RISC-V spec S-privileged registers remain in the first register
> range and are compatible with "riscv,iommu" so the Linux driver does not
> notice any difference, but the binding will be used by OpenSBI and
> potentially other M-mode software.
> 
> Reviewed-by: Joel Stanley <joel@jms.id.au>
> Acked-by: Joerg Roedel <joerg.roedel@amd.com>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> [fustini: fix dt_binding_check errors]
> Signed-off-by: Drew Fustini <fustini@kernel.org>
> ---
> v2 changes:
> - Fix dt_binding_check errors
> - Add the Acked-by: from Joerg
> - Drop RFC prefix
> 
> Link to v1:
> https://lore.kernel.org/lkml/20260310003850.3837030-1-npiggin@gmail.com/
> 
>  .../bindings/iommu/riscv,iommu.yaml           | 62 ++++++++++++++++---
>  1 file changed, 55 insertions(+), 7 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
> index d4838c3b3741..5aad8cf67840 100644
> --- a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
> @@ -32,22 +32,35 @@ properties:
>    # should be specified along with 'reg' property providing MMIO location.
>    compatible:
>      oneOf:
> -      - items:
> +      - description: Platform (non-PCIe) IOMMU implementations
> +        items:
>            - enum:
>                - qemu,riscv-iommu
>            - const: riscv,iommu
> -      - items:
> +      - description: PCIe IOMMU implementations
> +        items:
>            - enum:
>                - pci1efd,edf1
>            - const: riscv,pci-iommu
> +      - description: Tenstorrent IOMMUs implementing "riscv,iommu"
> +        items:
> +          - enum:
> +              - tenstorrent,riscv-iommu
> +          - const: riscv,iommu

You should be able to put this into the enum alongside the qemu
compatible, right?

>  
>    reg:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 2
>      description:
> -      For non-PCI devices this represents base address and size of for the
> -      IOMMU memory mapped registers interface.
> -      For PCI IOMMU hardware implementation this should represent an address
> -      of the IOMMU, as defined in the PCI Bus Binding reference.
> +      For non-PCI devices the first item represents base address and size of
> +      for the IOMMU memory mapped registers interface.
> +      For PCI IOMMU hardware implementation the first item should represent
> +      an address of the IOMMU, as defined in the PCI Bus Binding reference.
> +
> +  reg-names:
> +    items:
> +      - const: base
> +      - const: machine
>  
>    '#iommu-cells':
>      const: 1
> @@ -75,6 +88,31 @@ required:
>  
>  additionalProperties: false
>  
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - tenstorrent,riscv-iommu
> +    then:
> +      properties:
> +        reg:

> +          items:
> +            - description: IOMMU base registers
> +            - description: Tenstorrent IOMMU machine mode registers.

Should this also have minItems: 2?

> +        reg-names:

> +          items:
> +            - const: base
> +            - const: machine
> +              description:
> +                Region containing platform specific MMRs for machine-mode
> +                configuration, such as PMA and PMP registers.

And this you should replace with minItems: 2 or delete. The reg property
is where your description here belongs and all the names do here is
re-list what's available outside the condition.

> +    else:
> +      properties:
> +        reg:
> +          maxItems: 1
> +
>  examples:
>    - |+
>      /* Example 1 (IOMMU device with wired interrupts) */
> @@ -145,3 +183,13 @@ examples:
>              };
>          };
>      };
> +
> +  - |+
> +    /* Example 5 (Tenstorrent IOMMU device with MSIs) */
> +    iommu5: iommu@d2020000 {
> +        compatible = "tenstorrent,riscv-iommu", "riscv,iommu";
> +        reg = <0xd2020000 0x10000 0xaa000000 0x10000>;

This is not the correct format for multiple reg properties. Hint: you're
missing ">, <".

pw-bot: changes-requested

Cheers,
Conor.

> +        reg-names = "base", "machine";
> +        msi-parent = <&imsics_smode>;
> +        #iommu-cells = <1>;
> +    };
> -- 
> 2.43.0
> 

On Wed, May 20, 2026 at 05:17:41PM +0100, Conor Dooley wrote:

Thanks for the review...

> On Tue, May 19, 2026 at 11:16:28PM -0700, Drew Fustini wrote:
> > From: Nicholas Piggin <npiggin@gmail.com>
> > 
> > Extend the binding to cover details specific to the Tenstorrent RISC-V
> > IOMMU. In particular, a second register range is added which contains
> > M-privileged registers, e.g., PMAs and PMPs.
> > 
> > The RISC-V spec S-privileged registers remain in the first register
> > range and are compatible with "riscv,iommu" so the Linux driver does not
> > notice any difference, but the binding will be used by OpenSBI and
> > potentially other M-mode software.
> > 
> > Reviewed-by: Joel Stanley <joel@jms.id.au>
> > Acked-by: Joerg Roedel <joerg.roedel@amd.com>
> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> > [fustini: fix dt_binding_check errors]
> > Signed-off-by: Drew Fustini <fustini@kernel.org>
> > ---
> > v2 changes:
> > - Fix dt_binding_check errors
> > - Add the Acked-by: from Joerg
> > - Drop RFC prefix
> > 
> > Link to v1:
> > https://lore.kernel.org/lkml/20260310003850.3837030-1-npiggin@gmail.com/
> > 
> >  .../bindings/iommu/riscv,iommu.yaml           | 62 ++++++++++++++++---
> >  1 file changed, 55 insertions(+), 7 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
> > index d4838c3b3741..5aad8cf67840 100644
> > --- a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
> > +++ b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
> > @@ -32,22 +32,35 @@ properties:
> >    # should be specified along with 'reg' property providing MMIO location.
> >    compatible:
> >      oneOf:
> > -      - items:
> > +      - description: Platform (non-PCIe) IOMMU implementations
> > +        items:
> >            - enum:
> >                - qemu,riscv-iommu
> >            - const: riscv,iommu
> > -      - items:
> > +      - description: PCIe IOMMU implementations
> > +        items:
> >            - enum:
> >                - pci1efd,edf1
> >            - const: riscv,pci-iommu
> > +      - description: Tenstorrent IOMMUs implementing "riscv,iommu"
> > +        items:
> > +          - enum:
> > +              - tenstorrent,riscv-iommu
> > +          - const: riscv,iommu
> 
> You should be able to put this into the enum alongside the qemu
> compatible, right?

Good point, I'll move tenstorrent,riscv-iommu to the enum with
qemu,riscv-iommu.

> > +allOf:
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - tenstorrent,riscv-iommu
> > +    then:
> > +      properties:
> > +        reg:
> 
> > +          items:
> > +            - description: IOMMU base registers
> > +            - description: Tenstorrent IOMMU machine mode registers.
> 
> Should this also have minItems: 2?

I think items: with 2 items implies minItems: 2 but I see your later
point about the description and names don't belong in the allOf: block.

> 
> > +        reg-names:
> 
> > +          items:
> > +            - const: base
> > +            - const: machine
> > +              description:
> > +                Region containing platform specific MMRs for machine-mode
> > +                configuration, such as PMA and PMP registers.
> 
> And this you should replace with minItems: 2 or delete. The reg property
> is where your description here belongs and all the names do here is
> re-list what's available outside the condition.

Ah, so I just have minItems: 2 here and rely on the reg: section to have
the descriptions.

> > +  - |+
> > +    /* Example 5 (Tenstorrent IOMMU device with MSIs) */
> > +    iommu5: iommu@d2020000 {
> > +        compatible = "tenstorrent,riscv-iommu", "riscv,iommu";
> > +        reg = <0xd2020000 0x10000 0xaa000000 0x10000>;
> 
> This is not the correct format for multiple reg properties. Hint: you're
> missing ">, <".

Thanks, I'll fix that.

-Drew

On Wed, May 20, 2026 at 11:14:32AM -0700, Drew Fustini wrote:
> On Wed, May 20, 2026 at 05:17:41PM +0100, Conor Dooley wrote:
> > On Tue, May 19, 2026 at 11:16:28PM -0700, Drew Fustini wrote:
> > > +allOf:
> > > +  - if:
> > > +      properties:
> > > +        compatible:
> > > +          contains:
> > > +            enum:
> > > +              - tenstorrent,riscv-iommu
> > > +    then:
> > > +      properties:
> > > +        reg:
> > 
> > > +          items:
> > > +            - description: IOMMU base registers
> > > +            - description: Tenstorrent IOMMU machine mode registers.
> > 
> > Should this also have minItems: 2?
> 
> I think items: with 2 items implies minItems: 2 but I see your later
> point about the description and names don't belong in the allOf: block.

It would usually, but this is a conditional portion of a wider binding
that you've modified to look like
| reg:
|  minItems: 1
|  maxItems: 2
outside the conditional section, and since you don't further constrain
reg in the conditional section, this minItems: 1 applies.