This series fixes several issues in the atmel-hlcdc CRTC clock handling
and adds LVDS display support for XLCDC-based SoCs.

The first patch fixes a pre-existing off-by-one error in the vertical
back porch register calculation. The following patches progressively
clean up the clock divider logic by introducing DIV_ROUND_CLOSEST,
defining a named maximum divider constant, and extracting clock setup
into a dedicated helper. Clock bypass support is then added for XLCDC
hardware when the computed divider is less than 2.

The final two patches introduce LVDS PLL clock support, configuring the
PLL to 7x the pixel clock rate before the timing engine is programmed,
and add an LVDS output mode handler to map LVDS bus formats to the
appropriate display output modes.

Manikandan Muralidharan (7):
  drm: atmel-hlcdc: Fix off-by-one in vertical back porch setting
  drm: atmel-hlcdc: simplify clock divider selection with
    DIV_ROUND_CLOSEST
  drm: atmel-hlcdc: define ATMEL_HLCDC_CLKDIV_MAX and fix divider
    fallback
  drm: atmel-hlcdc: extract clock setup into a dedicated helper
  drm: atmel-hlcdc: add XLCDC clock bypass support for small dividers
  drm: atmel-hlcdc: add and configure LVDS PLL clock support
  drm: atmel-hlcdc: add LVDS output mode support

Ryan Wanner (1):
  drm: atmel-hlcdc: reorder timing register writes after clock setup

 .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c    | 190 +++++++++++++-----
 include/linux/mfd/atmel-hlcdc.h               |   2 +
 2 files changed, 139 insertions(+), 53 deletions(-)

-- 
2.25.1