Hi,

Quite awhile ago I reported
https://gitlab.freedesktop.org/drm/amd/-/work_items/4849 and it appears
that I'm the only unlucky soul to have this particular GPU/Display
combo.

Having some time off I decided to put these new fangled LLMs (GPT-5.5)
into the test, and it found the issue rather quickly: MISC1 bit 6 was
not set, causing the display to prefer MSA colorimetry. In the case
Windows was booted first, the Radeon driver there configured the sink
correctly, and it would keep that state until the link is disconnected.

The hypothesis was tested and verified by using `umr` to modify the
`DP_MSA_MISC` register directly, following with a display power-cycle.
The implementation was copied from the code path used for DCN-based
GPUs, and extra register wiring was assisted by LLM.

This is my very first patch into the kernel, and I don't have a lot of
experience with GPUs, so guidance would be greatly appreciated. If
possible, I would like this fix to go into the stable branch as well, so
I don't have to wait until the next release to use my monitor :D

-- Leorize

Leorize (1):
  drm/amd/display: set MSA MISC1 bit 6 when using VSC SDP for DCE 11.x

 .../drm/amd/display/dc/dce/dce_stream_encoder.c   | 15 ++++++++++++++-
 .../drm/amd/display/dc/dce/dce_stream_encoder.h   |  3 ++-
 2 files changed, 16 insertions(+), 2 deletions(-)

-- 
2.54.0