This series programs Synopsys DesignWare ASPM L1 entrance latency on NVIDIA
Tegra194/234 PCIe controllers from an optional device tree property and
corrects the default nanosecond cells so the PORT_AFR field advertises the
intended latency buckets.

Background
----------
The controller exposes L1 entrance latency in PCI Express PORT_AFR (DW DBI),
bits 27:29.  Software must select a 3-bit code for the maximum L1 entry delay
the platform can tolerate.  Patch 1 reads aspm-l1-entry-delay-ns (nanoseconds),
converts to whole microseconds with ceiling division (DIV_ROUND_UP), and
programs min(order_base_2(us), 7) into PORT_AFR during ASPM init.  If the
property is absent, the driver keeps the existing default (code 7).

PORT_AFR L1 entrance latency encoding (bits 27:29)
--------------------------------------------------
  +--------------------------+----------+
  | Advertised maximum       | Code     |
  +--------------------------+----------+
  | Maximum of 1 us          | 000b     |
  +--------------------------+----------+
  | Maximum of 2 us          | 001b     |
  +--------------------------+----------+
  | Maximum of 4 us          | 010b     |
  +--------------------------+----------+
  | Maximum of 8 us          | 011b     |
  +--------------------------+----------+
  | Maximum of 16 us         | 100b     |
  +--------------------------+----------+
  | Maximum of 32 us         | 101b     |
  +--------------------------+----------+
  | Maximum of 64 us         | 110b     |
  +--------------------------+----------+
  | Rest                     | 111b     |
  +--------------------------+----------+

Patch summary
-------------
 1/2  PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance
      latency

      Add driver support described above.  v1 and v2 could not program
      encoding 0 (000b, 1 us bucket); v3 uses order_base_2(us) so values map
      to the table.

 2/2  arm64: tegra: fix aspm-l1-entry-delay-ns L1 latency cells

      Commit d60ed99f1c9e ("arm64: tegra: Add aspm-l1-entry-delay-ns to PCIe
      nodes") added 4000 / 8000 / 16000 ns cells.  After ceiling conversion
      those are 4 / 8 / 16 us, yielding PORT_AFR codes 2 / 3 / 4.  The
      intended advertisement is codes 3 / 4 / 5 (8 / 16 / 32 us buckets).
      Double each nanosecond cell:

        tegra194.dtsi: 4000 -> 8000 ns (all Root Port and Endpoint nodes)
        tegra234.dtsi: 8000 -> 16000 ns (Root Port), 16000 -> 32000 ns (Endpoint)

      With the v3 driver mapping in place, the original nanosecond cells no
      longer yield the intended PORT_AFR codes; doubling them restores codes
      3 / 4 / 5 as described above.

      Fixes: d60ed99f1c9e ("arm64: tegra: Add aspm-l1-entry-delay-ns to PCIe nodes")

Testing
-------
 - Verified device tree parsing and PORT_AFR encoding on target hardware.
 - Exercised boundary nanosecond values with a temporary debug patch.
 - Built on x86_64 (previous revision exposed a tree build failure).

Manikanta Maddireddy (2):
  PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance
    latency
  arm64: tegra: fix aspm-l1-entry-delay-ns L1 latency cells

 arch/arm64/boot/dts/nvidia/tegra194.dtsi   | 18 ++++++------
 arch/arm64/boot/dts/nvidia/tegra234.dtsi   | 32 +++++++++++-----------
 drivers/pci/controller/dwc/pcie-tegra194.c | 13 +++++++++
 3 files changed, 38 insertions(+), 25 deletions(-)

-- 
2.34.1

From: Thierry Reding <treding@nvidia.com>


On Fri, 15 May 2026 12:37:51 +0530, Manikanta Maddireddy wrote:
> This series programs Synopsys DesignWare ASPM L1 entrance latency on NVIDIA
> Tegra194/234 PCIe controllers from an optional device tree property and
> corrects the default nanosecond cells so the PORT_AFR field advertises the
> intended latency buckets.
> 
> Background
> ----------
> The controller exposes L1 entrance latency in PCI Express PORT_AFR (DW DBI),
> bits 27:29.  Software must select a 3-bit code for the maximum L1 entry delay
> the platform can tolerate.  Patch 1 reads aspm-l1-entry-delay-ns (nanoseconds),
> converts to whole microseconds with ceiling division (DIV_ROUND_UP), and
> programs min(order_base_2(us), 7) into PORT_AFR during ASPM init.  If the
> property is absent, the driver keeps the existing default (code 7).
> 
> [...]

Applied, thanks!

[2/2] arm64: tegra: fix aspm-l1-entry-delay-ns L1 latency cells
      commit: 56c5f525817ea99ce34110700b3a0ab71add0b8c

Best regards,
-- 
Thierry Reding <treding@nvidia.com>

On Fri, 15 May 2026 12:37:51 +0530, Manikanta Maddireddy wrote:
> This series programs Synopsys DesignWare ASPM L1 entrance latency on NVIDIA
> Tegra194/234 PCIe controllers from an optional device tree property and
> corrects the default nanosecond cells so the PORT_AFR field advertises the
> intended latency buckets.
> 
> Background
> ----------
> The controller exposes L1 entrance latency in PCI Express PORT_AFR (DW DBI),
> bits 27:29.  Software must select a 3-bit code for the maximum L1 entry delay
> the platform can tolerate.  Patch 1 reads aspm-l1-entry-delay-ns (nanoseconds),
> converts to whole microseconds with ceiling division (DIV_ROUND_UP), and
> programs min(order_base_2(us), 7) into PORT_AFR during ASPM init.  If the
> property is absent, the driver keeps the existing default (code 7).
> 
> [...]

Applied, thanks!

[1/2] PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency
      commit: 87f493041e20759ffc27262cc0490c41628a5ee2

Best regards,
-- 
Manivannan Sadhasivam <mani@kernel.org>