QUP1_SE4 uses GPIO36 and GPIO37 for two selectable lane pairs.
Splitting into function per lane works, but it forces the devicetree to
describe a state per pin while these are usually configured in pairs.

Follow the pair-wise scheme used on Qualcomm Hawi platform and expose
the two selectable pairs as qup1_se4_01 and qup1_se4_23 in both the
binding and the driver.

This has been proposed here:
https://lore.kernel.org/all/agIZOAa6nYSb5PWX@baldur/

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
Changes in v2:
- Explicitly mentioned "per-lane qup1_se4_l[0-3] names" in the
  bindings commit message, as Krzysztof suggested.
- Picked up Krzysztof's A-b tag for the bindings patch.
- Link to v1: https://patch.msgid.link/20260513-eliza-tlmm-group-qup1-se4-lanes-v1-0-1babc6118829@oss.qualcomm.com

---
Abel Vesa (2):
      dt-bindings: pinctrl: qcom,eliza-tlmm: Merge QUP1_SE4 lane functions
      pinctrl: qcom: eliza: Merge QUP1_SE4 lanes in groups

 .../bindings/pinctrl/qcom,eliza-tlmm.yaml          |  4 +--
 drivers/pinctrl/qcom/pinctrl-eliza.c               | 32 +++++++---------------
 2 files changed, 12 insertions(+), 24 deletions(-)
---
base-commit: e98d21c170b01ddef366f023bbfcf6b31509fa83
change-id: 20260513-eliza-tlmm-group-qup1-se4-lanes-2861e6928685

Best regards,
--  
Abel Vesa <abel.vesa@oss.qualcomm.com>

On Fri, May 15, 2026 at 1:22 PM Abel Vesa <abel.vesa@oss.qualcomm.com> wrote:

> QUP1_SE4 uses GPIO36 and GPIO37 for two selectable lane pairs.
> Splitting into function per lane works, but it forces the devicetree to
> describe a state per pin while these are usually configured in pairs.
>
> Follow the pair-wise scheme used on Qualcomm Hawi platform and expose
> the two selectable pairs as qup1_se4_01 and qup1_se4_23 in both the
> binding and the driver.
>
> This has been proposed here:
> https://lore.kernel.org/all/agIZOAa6nYSb5PWX@baldur/
>
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

Patches applied!

Yours,
Linus Walleij

On Fri, May 15, 2026 at 02:21:50PM +0300, Abel Vesa wrote:
> QUP1_SE4 uses GPIO36 and GPIO37 for two selectable lane pairs.
> Splitting into function per lane works, but it forces the devicetree to
> describe a state per pin while these are usually configured in pairs.
> 
> Follow the pair-wise scheme used on Qualcomm Hawi platform and expose
> the two selectable pairs as qup1_se4_01 and qup1_se4_23 in both the
> binding and the driver.
> 

Given how fresh this binding is, I think it's okay to make the change.

Reviewed-by: Bjorn Andersson <andersson@kernel.org>

Regards,
Bjorn

> This has been proposed here:
> https://lore.kernel.org/all/agIZOAa6nYSb5PWX@baldur/
> 
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
> Changes in v2:
> - Explicitly mentioned "per-lane qup1_se4_l[0-3] names" in the
>   bindings commit message, as Krzysztof suggested.
> - Picked up Krzysztof's A-b tag for the bindings patch.
> - Link to v1: https://patch.msgid.link/20260513-eliza-tlmm-group-qup1-se4-lanes-v1-0-1babc6118829@oss.qualcomm.com
> 
> ---
> Abel Vesa (2):
>       dt-bindings: pinctrl: qcom,eliza-tlmm: Merge QUP1_SE4 lane functions
>       pinctrl: qcom: eliza: Merge QUP1_SE4 lanes in groups
> 
>  .../bindings/pinctrl/qcom,eliza-tlmm.yaml          |  4 +--
>  drivers/pinctrl/qcom/pinctrl-eliza.c               | 32 +++++++---------------
>  2 files changed, 12 insertions(+), 24 deletions(-)
> ---
> base-commit: e98d21c170b01ddef366f023bbfcf6b31509fa83
> change-id: 20260513-eliza-tlmm-group-qup1-se4-lanes-2861e6928685
> 
> Best regards,
> --  
> Abel Vesa <abel.vesa@oss.qualcomm.com>
>