Fix a variety of bugs in SVM's handling of x2APIC MSR passthrough for x2AVIC,
where KVM disables interception for MSR accesses that aren't accelerated by
hardware (pointless and suboptimal), and also does NOT disable interception
for practically any of the "range of vectors" MSRs, i.e. IRR, ISR, and TMR.

Note, I tagged all of this for stable, but I could be convinced these fixes
shouldn't be sent to LTS trees, as there are no functional bugs being fixed.

v3:
 - Consolidate list generation for APICv and x2AVIC RDMSR passthrough (and
   avoid the wonky post-iteration fixup in the process). [Naveen]
 - Collect reviews. [Naveen]
 - Drop the hacky selftest (it's still available in v2).
 - Massage the changelog for patch 3 to call out that at least one section
   of the APM does document that #GP has priority over the AVIC checks.
   [Naveen]
 - Document the impact on TMCCT in patch 2. [Naveen]

v2:
 - https://lore.kernel.org/all/20260506184746.2719880-1-seanjc@google.com
 - Actually iterate over the mask of readable regs. [Naveen]
 - Rewrite the changelog for patch 3 to more accurately capture what happens,
   and to avoid conflating "unaccelerated" with "fault-like". [Naveen]
 - Massage the changlog for patch 1 to describe the observed behavior of
   DFR and ICR2.
 - Test the #VMEXIT (or not) behavior with hacks (patches 4 and 5).

v1: https://lore.kernel.org/all/20260409222449.2013847-1-seanjc@google.com

Sean Christopherson (3):
  KVM: x86: Add dedicated API for getting mask of accelerated x2APIC
    MSRs
  KVM: SVM: Disable x2AVIC RDMSR interception for MSRs KVM actually
    supports
  KVM: SVM: Only disable x2AVIC WRMSR interception for MSRs that are
    accelerated

 arch/x86/kvm/lapic.c    | 21 ++++++++++++++++--
 arch/x86/kvm/lapic.h    |  2 +-
 arch/x86/kvm/svm/avic.c | 47 +++++++++++------------------------------
 arch/x86/kvm/vmx/vmx.c  |  3 +--
 4 files changed, 33 insertions(+), 40 deletions(-)


base-commit: a9512a611bd030088f13477258d1f8103cceaa40
-- 
2.54.0.563.g4f69b47b94-goog