The comment next to AD7192_REG_GPOCON marks the register as RO,
but the AD7192 datasheet (Rev. A, page 24, GPOCON REGISTER) says:
"The GPOCON register is an 8-bit register from which data can be
read or to which data can be written."

The driver itself uses ad_sd_write_reg() against this register in
ad7192_show_scale() / write paths to control the bridge power-down
switch and digital outputs, which matches the RW datasheet
description. Update the comment to RW so it does not mislead
future readers.

Signed-off-by: Stepan Ionichev <sozdayvek@gmail.com>
---
 drivers/iio/adc/ad7192.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/ad7192.c b/drivers/iio/adc/ad7192.c
index 8b1664f6b..98c1420a9 100644
--- a/drivers/iio/adc/ad7192.c
+++ b/drivers/iio/adc/ad7192.c
@@ -39,7 +39,7 @@
 #define AD7192_REG_CONF		2 /* Configuration Register  (RW, 24-bit) */
 #define AD7192_REG_DATA		3 /* Data Register	     (RO, 24/32-bit) */
 #define AD7192_REG_ID		4 /* ID Register	     (RO, 8-bit) */
-#define AD7192_REG_GPOCON	5 /* GPOCON Register	     (RO, 8-bit) */
+#define AD7192_REG_GPOCON	5 /* GPOCON Register	     (RW, 8-bit) */
 #define AD7192_REG_OFFSET	6 /* Offset Register	     (RW, 16-bit */
 				  /* (AD7792)/24-bit (AD7192)) */
 #define AD7192_REG_FULLSALE	7 /* Full-Scale Register */
-- 
2.43.0

On Wed, May 13, 2026 at 03:13:32PM +0500, Stepan Ionichev wrote:
> The comment next to AD7192_REG_GPOCON marks the register as RO,
> but the AD7192 datasheet (Rev. A, page 24, GPOCON REGISTER) says:
> "The GPOCON register is an 8-bit register from which data can be
> read or to which data can be written."
> 
> The driver itself uses ad_sd_write_reg() against this register in
> ad7192_show_scale() / write paths to control the bridge power-down
> switch and digital outputs, which matches the RW datasheet
> description. Update the comment to RW so it does not mislead
> future readers.

Makes sense,
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>

-- 
With Best Regards,
Andy Shevchenko

On Wed, 13 May 2026 16:35:30 +0300
Andy Shevchenko <andriy.shevchenko@intel.com> wrote:

> On Wed, May 13, 2026 at 03:13:32PM +0500, Stepan Ionichev wrote:
> > The comment next to AD7192_REG_GPOCON marks the register as RO,
> > but the AD7192 datasheet (Rev. A, page 24, GPOCON REGISTER) says:
> > "The GPOCON register is an 8-bit register from which data can be
> > read or to which data can be written."
> > 
> > The driver itself uses ad_sd_write_reg() against this register in
> > ad7192_show_scale() / write paths to control the bridge power-down
> > switch and digital outputs, which matches the RW datasheet
> > description. Update the comment to RW so it does not mislead
> > future readers.  
> 
> Makes sense,
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
> 

Applied to the testing branch of iio.git.

thanks,

Jonathan