Add support for the Last Level Cache Controller found on the Qualcomm
Eliza SoC.

Eliza's LLCC uses a 4-region register layout, with two per-bank base
regions plus the broadcast OR and AND windows.

Describe that layout in the devicetree bindings and add the corresponding
slice configuration and driver data in llcc-qcom.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
Changes in v2:
- Rebased on next-20260508.
- Replaced the weird phrase in the last commit with something
  more sane.
- Picked up Konrad's R-b tag for the second patch.
- Link to v1: https://patch.msgid.link/20260504-eliza-llcc-v1-0-d7006c899812@oss.qualcomm.com

---
Abel Vesa (2):
      dt-bindings: cache: qcom,llcc: Document Eliza LLCC block
      soc: qcom: llcc-qcom: Add support for Eliza

 .../devicetree/bindings/cache/qcom,llcc.yaml       |  22 +++
 drivers/soc/qcom/llcc-qcom.c                       | 180 +++++++++++++++++++++
 2 files changed, 202 insertions(+)
---
base-commit: e98d21c170b01ddef366f023bbfcf6b31509fa83
change-id: 20260428-eliza-llcc-312b07fefc10

Best regards,
--  
Abel Vesa <abel.vesa@oss.qualcomm.com>

On Wed, 13 May 2026 14:11:01 +0300, Abel Vesa wrote:
> Add support for the Last Level Cache Controller found on the Qualcomm
> Eliza SoC.
> 
> Eliza's LLCC uses a 4-region register layout, with two per-bank base
> regions plus the broadcast OR and AND windows.
> 
> Describe that layout in the devicetree bindings and add the corresponding
> slice configuration and driver data in llcc-qcom.
> 
> [...]

Applied, thanks!

[1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block
      commit: 6487b12a875a5e3cc2f99ff7eba1112fe3f72483
[2/2] soc: qcom: llcc-qcom: Add support for Eliza
      commit: 0a4d53ae2cb68cbfe3c69e14d8cfc0acc7c37bda

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>