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[PATCH] drivers: altera_edac: Fix OCRAM ECC init for warm reset

muhammad.nazim.amirul.nazle.asmade@altera.com posted 1 patch 1 month ago 
drivers/edac/altera_edac.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
[PATCH] drivers: altera_edac: Fix OCRAM ECC init for warm reset
Posted by muhammad.nazim.amirul.nazle.asmade@altera.com 1 month ago 
From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

The OCRAM ECC is always enabled either by the BootROM or by the
Secure Device Manager (SDM) during a power-on reset on SoCFPGA.

However, during a warm reset, the OCRAM content is retained to
preserve data, while the control and status registers are reset to
their default values. As a result, ECC must be explicitly re-enabled
after a warm reset.

Signed-off-by: Niravkumar L Rabara <nirav.rabara@altera.com>
Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
 drivers/edac/altera_edac.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 103b2c2eba2a..9e6a9786a881 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1186,8 +1186,14 @@ altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
 
 	/* Verify OCRAM has been initialized */
 	if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
-			   (base + ALTR_A10_ECC_INITSTAT_OFST)))
-		return -ENODEV;
+			   (base + ALTR_A10_ECC_INITSTAT_OFST))) {
+		if (!ecc_test_bits(ALTR_A10_ECC_EN,
+				   (base + ALTR_A10_ECC_CTRL_OFST)))
+			ecc_set_bits(ALTR_A10_ECC_EN,
+				     (base + ALTR_A10_ECC_CTRL_OFST));
+		else
+			return -ENODEV;
+	}
 
 	/* Enable IRQ on Single Bit Error */
 	writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));
-- 
2.43.7
Re: [PATCH] drivers: altera_edac: Fix OCRAM ECC init for warm reset
Posted by Dinh Nguyen 1 month ago 

On 5/9/26 09:38, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
> 
> The OCRAM ECC is always enabled either by the BootROM or by the
> Secure Device Manager (SDM) during a power-on reset on SoCFPGA.
> 
> However, during a warm reset, the OCRAM content is retained to
> preserve data, while the control and status registers are reset to
> their default values. As a result, ECC must be explicitly re-enabled
> after a warm reset.
> 
> Signed-off-by: Niravkumar L Rabara <nirav.rabara@altera.com>
> Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
> ---
>   drivers/edac/altera_edac.c | 10 ++++++++--
>   1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
> index 103b2c2eba2a..9e6a9786a881 100644
> --- a/drivers/edac/altera_edac.c
> +++ b/drivers/edac/altera_edac.c
> @@ -1186,8 +1186,14 @@ altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
>   
>   	/* Verify OCRAM has been initialized */
>   	if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
> -			   (base + ALTR_A10_ECC_INITSTAT_OFST)))
> -		return -ENODEV;
> +			   (base + ALTR_A10_ECC_INITSTAT_OFST))) {
> +		if (!ecc_test_bits(ALTR_A10_ECC_EN,
> +				   (base + ALTR_A10_ECC_CTRL_OFST)))
> +			ecc_set_bits(ALTR_A10_ECC_EN,
> +				     (base + ALTR_A10_ECC_CTRL_OFST));
> +		else
> +			return -ENODEV;
> +	}
>   
>   	/* Enable IRQ on Single Bit Error */
>   	writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));

This patch fails to apply to both v7.1-rc1 and linux-next. Please base 
your patch to the latest and resend.

Thanks,
Dinh
Re: [PATCH] drivers: altera_edac: Fix OCRAM ECC init for warm reset
Posted by Nazle Asmade, Muhammad Nazim Amirul 1 month ago 
On 11/5/2026 4:31 am, Dinh Nguyen wrote:
> 
> 
> On 5/9/26 09:38, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
>> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
>>
>> The OCRAM ECC is always enabled either by the BootROM or by the
>> Secure Device Manager (SDM) during a power-on reset on SoCFPGA.
>>
>> However, during a warm reset, the OCRAM content is retained to
>> preserve data, while the control and status registers are reset to
>> their default values. As a result, ECC must be explicitly re-enabled
>> after a warm reset.
>>
>> Signed-off-by: Niravkumar L Rabara <nirav.rabara@altera.com>
>> Signed-off-by: Nazim Amirul 
>> <muhammad.nazim.amirul.nazle.asmade@altera.com>
>> ---
>>   drivers/edac/altera_edac.c | 10 ++++++++--
>>   1 file changed, 8 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
>> index 103b2c2eba2a..9e6a9786a881 100644
>> --- a/drivers/edac/altera_edac.c
>> +++ b/drivers/edac/altera_edac.c
>> @@ -1186,8 +1186,14 @@ altr_check_ocram_deps_init(struct 
>> altr_edac_device_dev *device)
>>       /* Verify OCRAM has been initialized */
>>       if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
>> -               (base + ALTR_A10_ECC_INITSTAT_OFST)))
>> -        return -ENODEV;
>> +               (base + ALTR_A10_ECC_INITSTAT_OFST))) {
>> +        if (!ecc_test_bits(ALTR_A10_ECC_EN,
>> +                   (base + ALTR_A10_ECC_CTRL_OFST)))
>> +            ecc_set_bits(ALTR_A10_ECC_EN,
>> +                     (base + ALTR_A10_ECC_CTRL_OFST));
>> +        else
>> +            return -ENODEV;
>> +    }
>>       /* Enable IRQ on Single Bit Error */
>>       writel(ALTR_A10_ECC_SERRINTEN, (base + 
>> ALTR_A10_ECC_ERRINTENS_OFST));
> 
> This patch fails to apply to both v7.1-rc1 and linux-next. Please base 
> your patch to the latest and resend.
> 
> Thanks,
> Dinh
> 
sorry for this confusion, dropping this patch as already available in 
upstream
Re: [PATCH] drivers: altera_edac: Fix OCRAM ECC init for warm reset
Posted by Borislav Petkov 1 month ago 
On Sun, May 10, 2026 at 03:31:56PM -0500, Dinh Nguyen wrote:
> 
> 
> On 5/9/26 09:38, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
> > From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
> > 
> > The OCRAM ECC is always enabled either by the BootROM or by the
> > Secure Device Manager (SDM) during a power-on reset on SoCFPGA.
> > 
> > However, during a warm reset, the OCRAM content is retained to
> > preserve data, while the control and status registers are reset to
> > their default values. As a result, ECC must be explicitly re-enabled
> > after a warm reset.
> > 
> > Signed-off-by: Niravkumar L Rabara <nirav.rabara@altera.com>
> > Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

And fix your SOB chain:

https://kernel.org/doc/html/latest/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin

From the above, I have no clue what Niravkumar has done.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

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