[PATCH v2 0/3] PCI: cadence: Fix and generalize PCIe capability offset for Root Port

Hans Zhang posted 3 patches 1 month ago
.../pci/controller/cadence/pcie-cadence-ep.c  |  5 +--
.../cadence/pcie-cadence-host-common.c        |  4 +--
.../cadence/pcie-cadence-host-hpa.c           |  2 ++
.../controller/cadence/pcie-cadence-host.c    |  6 ++--
.../cadence/pcie-cadence-lga-regs.h           |  1 -
drivers/pci/controller/cadence/pcie-cadence.h | 31 ++++++++++++++++++-
6 files changed, 41 insertions(+), 8 deletions(-)
[PATCH v2 0/3] PCI: cadence: Fix and generalize PCIe capability offset for Root Port
Posted by Hans Zhang 1 month ago
The Cadence PCIe controller has two major IP generations: LGA (Legacy)
and HPA. In Root Port mode, their configuration space base addresses
differ (LGA requires an offset of 0x200000, HPA uses 0). Moreover, the
PCI Express Capability structure may not reside at the hardcoded offset
0xC0 across all SoC integrations.

This series fixes the Root Port configuration space accessors to
correctly handle the base offset on LGA IP, then introduces a helper
to dynamically find and cache the PCIe Capability offset, and finally
replaces all hardcoded uses of CDNS_PCIE_RP_CAP_OFFSET with the cached
value.

Patch 1 fixes the fundamental read accessors for RC mode on LGA IP.
Patch 2 adds the caching helper.
Patch 3 removes the hardcoded offset and uses the dynamic one.

These changes have been tested on:
- LGA-based platform (TI J7200, J721E) - confirmed by Aksh Garg.
- HPA-based platform (CIX Sky1) - capability search works normal.

Note: This series depends on the previously submitted "is_hpa" flag
introduction:
https://patchwork.kernel.org/project/linux-pci/patch/20260508034101.1910036-1-18255117159@163.com/

Changes since v1:
- Fixed critical bug in cdns_pcie_get_pcie_cap() where dw_pcie types
  were incorrectly used (suggested by Bjorn Helgaas).
- Corrected function comment and parameter description.
- Added defensive check (not included in this version, but recommended).

Hans Zhang (3):
  PCI: cadence: Fix Root Port configuration space access for LGA IP
  PCI: cadence: Add cdns_pcie_get_pcie_cap() helper and cache capability
    offset
  PCI: cadence: Use dynamic PCIe capability offset in host driver

 .../pci/controller/cadence/pcie-cadence-ep.c  |  5 +--
 .../cadence/pcie-cadence-host-common.c        |  4 +--
 .../cadence/pcie-cadence-host-hpa.c           |  2 ++
 .../controller/cadence/pcie-cadence-host.c    |  6 ++--
 .../cadence/pcie-cadence-lga-regs.h           |  1 -
 drivers/pci/controller/cadence/pcie-cadence.h | 31 ++++++++++++++++++-
 6 files changed, 41 insertions(+), 8 deletions(-)


base-commit: 917719c412c48687d4a176965d1fa35320ec457c
prerequisite-patch-id: 2db32bc3c7b72f1206f365606060da203bfd683a
prerequisite-patch-id: f37881f3d5564b7bdd5e0aee093a297e3e0a79c0
-- 
2.34.1