Rework the handling of PEBS_ENABLED (and related PEBS MSRs) to *never* touch
PEBS_ENABLED if the CPU provides PEBS isolation, in which case disabling
counters via PERF_GLOBAL_CTRL is sufficient to prevent generation of unwanted
PEBS records. For vCPUs without PEBS enabled, this saves upwards of 7 MSR
writes on each roundtrip between the guest and host (KVM performs an immediate
WRMSR to zero out PEBS_ENABLED if it's in the load list). For vCPUS with PEBS,
this saves 3 MSR writes per roundtrip.
E.g. without PEBS activity in the host, for a guest with a vPMU, this reduces
the roundtrip time for a fastpath exit from ~1120 => ~860 cycles on EMR. With
host PEBS active, the reduction is ~1450 => ~900 cycles.
However, performance isn't the underlying motiviation (well, at least, it
didn't start that way). Jim, Mingwei, and Stephane have been chasing issues
where PEBS_ENABLED bits can get "stuck" in a '1' state when running KVM guests
while profiling the host with PEBS events. The working theory is that perf
throttles PEBS events in NMI context, and thus clears bits in cpuc->pebs_enabled
and PEBS_ENABLED, after generating the list of PMU MSRs to context switch but
before VM-Entry. And so when the host's PEBS_ENABLED is loaded on VM-Exit, the
CPU ends up with a stale PEBS_ENABLED that doesn't get reset until something
triggers an explicit reload in perf.
Note, as Peter pointed out, more than likely KVM needs to zero PERF_GLOBAL_CTRL
before invoking perf_guest_get_msrs(), as that's the only way to guarantee
stable output. I deliberately didn't include that here, as I want to keep this
series focused on PEBS. I also wanted to let Jim and company bottom out on
their investigation (still ongoing) before pursuing fixes that we'll probably
want to send to stable@.
v3:
- Ensure guest PEBS_ENABLE is a subset of intel_ctrl. [Jim]
- Rename intel_ctrl_{guest,host}_mask to be less confusing. [Jim]
- Do even more cleanup of the cross-mapped handling, and specifically avoid
overhead when PEBS isn't in use. [Sashiko]
- Leave behind a FIXME regarding the "disable guest PEBS if host is using
PEBS" code. I still don't know for sure why that restriction is in place,
and I'm too scared too change it. :-)
v2:
- https://lore.kernel.org/all/20260423150340.463896-1-seanjc@google.com
- "Load" the host value for the guest when an MSR should remain unchanged,
instead of omitting the MSR from the list entirely, as KVM may need to
_remove_ the MSR from the list. [Sashiko, Jim]
- Collect Jim's reviews. [Jim]
- Call out that the bug being fixed is theoretical at this point.
- Dropping PEBS_ENABLED from the lists save three MSR writes, not two, as
KVM performs an explicit WRMSR prior to VM-Entry to guarantee PEBS is
quiesced.
v1: https://lore.kernel.org/all/20260414191425.2697918-1-seanjc@google.com
Sean Christopherson (9):
perf/x86/intel: Ensure guest PEBS path doesn't set unwanted
PERF_GLOBAL_CTRL bits
perf/x86/intel: Don't write PEBS_ENABLED on host<=>guest xfers if CPU
has isolation
perf/x86/intel: Don't context switch DS_AREA (and PEBS config) if PEBS
is unused
perf/x86/intel: Make @data a mandatory param for
intel_guest_get_msrs()
perf/x86/intel: Invert names of intel_ctrl_{guest,host}_mask
perf/x86: KVM: Have perf define a dedicated struct for getting guest
PEBS data
perf/x86/intel: KVM: Handle cross-mapped PEBS PMCs entirely within KVM
KVM: VMX: Drop a redundant pmu->global_ctrl check when processing
pebs_enable
KVM: VMX: Only tell perf to enable PEBS counters for fully enabled
PMCs
arch/x86/events/core.c | 5 +-
arch/x86/events/intel/core.c | 92 +++++++++++++++++++------------
arch/x86/events/intel/lbr.c | 2 +-
arch/x86/events/perf_event.h | 7 ++-
arch/x86/include/asm/kvm_host.h | 9 ---
arch/x86/include/asm/perf_event.h | 11 +++-
arch/x86/kvm/vmx/pmu_intel.c | 28 +++++++---
arch/x86/kvm/vmx/vmx.c | 10 ++--
arch/x86/kvm/vmx/vmx.h | 15 ++++-
9 files changed, 114 insertions(+), 65 deletions(-)
base-commit: 254f49634ee16a731174d2ae34bc50bd5f45e731
--
2.54.0.563.g4f69b47b94-goog