From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
The Agilex5 SoC provides RGMII TX/RX clock delay compensation through
its integrated I/O hardware. Using phy-mode = "rgmii-id" instructs the
MAC driver to additionally insert internal TX/RX delays, resulting in
double delay being applied and causing Ethernet link timing issues.
Change phy-mode to "rgmii" across all Agilex5 device tree files to
reflect that the clock delay is already handled by the hardware and
no additional software-inserted delay is required. Add an inline comment
to satisfy checkpatch and document the hardware-provided delay.
Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 2 +-
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts | 2 +-
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts | 2 +-
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index 262bb3e8e5c7..bf0dbcd89f72 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -42,7 +42,7 @@ &gpio0 {
&gmac2 {
status = "okay";
- phy-mode = "rgmii-id";
+ phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */
phy-handle = <&emac2_phy0>;
max-frame-size = <9000>;
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
index f71e1280c778..cd1e545403e7 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
@@ -41,7 +41,7 @@ memory@80000000 {
&gmac2 {
status = "okay";
- phy-mode = "rgmii-id";
+ phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */
phy-handle = <&emac2_phy0>;
max-frame-size = <9000>;
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
index 1831402d8808..3a54fb14910d 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
@@ -44,7 +44,7 @@ &gpio1 {
&gmac2 {
status = "okay";
- phy-mode = "rgmii-id";
+ phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */
phy-handle = <&emac2_phy0>;
max-frame-size = <9000>;
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
index ec4541d44c9b..877e0090cf9b 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
@@ -39,7 +39,7 @@ memory@80000000 {
&gmac0 {
status = "okay";
- phy-mode = "rgmii-id";
+ phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */
phy-handle = <&emac0_phy0>;
max-frame-size = <9000>;
--
2.43.7