From: Biju Das <biju.das.jz@bp.renesas.com>

The RZ/G3L SOC has 3 watchdog timer channels:
 wdt channel0(wdt0) for Cortex-A55-CPU Non-Secure
 wdt channel1(wdt1) for Cortex-A55 CPU Secure
 wdt channel2(wdt2) for Cortex-M33 CPU

Enable wdt0 on RZ/G3L SMARC EVK platform.

This patch depend upon the binding patch[1] and [2]
[1] https://lore.kernel.org/all/20260206112227.233229-1-biju.das.jz@bp.renesas.com/
[2] https://lore.kernel.org/all/20260505123708.134069-1-biju.das.jz@bp.renesas.com/T/#t

Biju Das (2):
  arm64: dts: renesas: r9a08g046: Add wdt device node
  arm64: dts: renesas: rzg3l-smarc-som: Enable watchdog

 arch/arm64/boot/dts/renesas/r9a08g046.dtsi       | 14 ++++++++++++++
 arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi |  5 +++++
 2 files changed, 19 insertions(+)

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2.43.0