Add support for the Last Level Cache Controller found on the Qualcomm
Eliza SoC.

Eliza's LLCC uses a 4-region register layout, with two per-bank base
regions plus the broadcast OR and AND windows.

Describe that layout in the devicetree bindings and add the corresponding
slice configuration and driver data in llcc-qcom.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
Abel Vesa (2):
      dt-bindings: cache: qcom,llcc: Document Eliza LLCC block
      soc: qcom: llcc-qcom: Add support for Eliza

 .../devicetree/bindings/cache/qcom,llcc.yaml       |  22 +++
 drivers/soc/qcom/llcc-qcom.c                       | 180 +++++++++++++++++++++
 2 files changed, 202 insertions(+)
---
base-commit: b9303e6bff706758c167af686b5315ad00233bf8
change-id: 20260428-eliza-llcc-312b07fefc10

Best regards,
--  
Abel Vesa <abel.vesa@oss.qualcomm.com>