From: Biju Das <biju.das.jz@bp.renesas.com>

This patch series extends the RZ/G3L SMARC EVK platform to add OPP
table, IA55 and pin control support for Ethernet and SCIF0.

Patch 1 adds an OPP table for the RZ/G3L SoC, defining six operating
points ranging from 37.5 MHz to 1.2 GHz, and links each of the four
CA55 CPU cores to the OPP table along with their respective clocks.

Patch 2 adds the Interrupt Control Unit node to the RZ/G3L SoC DTSI,
wiring up the NMI, IRQ, TINT, and other interrupt sources to the GIC.

Patch 3 completes the pin controller node by adding the compatible
string, GPIO ranges, interrupt controller properties, clock, resets,
and the clone channel reference, and sets the ICU as the
interrupt-parent of the pin controller.

Patch 4 adds SCIF0 pin control configuration to the RZ/G3L SMARC board
DTS.

Patch 5 adds pin control configuration for the ETH0 Gigabit Ethernet
interface on the RZ/G3L SMARC SoM, including RGMII pin muxing and
hotplug interrupt support via the ICU.

Patch 6 enables the second Gigabit Ethernet interface (GBETH1/ETH1) on
the RZ/G3L SMARC SoM, adding its pin control configuration and PHY
settings mirroring those of ETH0.

This patch series depends upon [1], which has no further dependencies as
all the prerequisite patches have been accepted.

v2->v3:
 * Split from [2].
 * Added ICU node and set ICU as the interrupt-parent of the pin
   controller.
 * Moved ETH0 pin control support to a separate patch.
 * Dropped ethernet-phy-ieee802.3-c22 from mdio1 device node.
 * Fixed typo txdv-skew-psec -> txen-skew-psec.
 * Added hotplug support for ethernet.
 * Renamed SCIF_{RXD,TXD} -> SCIF0_{RXD,TXD} pins.
 * Added patch for OPP table support for RZ/G3L SoC
v1->v2:
  * Split DTSI patches from bindings
  * Fix typo maxItems->minItems in bindings
  * Collected the tag

[1] https://lore.kernel.org/all/20260326111953.31024-1-biju.das.jz@bp.renesas.com/
[2] https://lore.kernel.org/all/20260203131048.421708-1-biju.das.jz@bp.renesas.com/

Biju Das (6):
  arm64: dts: renesas: r9a08g046: Add OPP table
  arm64: dts: renesas: r9a08g046: Add ICU node
  arm64: dts: renesas: r9a08g046: Add pincontrol node
  arm64: dts: renesas: r9a08g046l48-smarc: Add SCIF0 pincontrol
  arm64: dts: renesas: rzg3l-smarc-som: Add pinctrl configuration for
    ETH0
  arm64: dts: renesas: rzg3l-smarc-som: Enable eth1 (GBETH1) interface

 arch/arm64/boot/dts/renesas/r9a08g046.dtsi    | 147 +++++++++++++++++-
 .../boot/dts/renesas/r9a08g046l48-smarc.dts   |  13 ++
 .../boot/dts/renesas/rzg3l-smarc-som.dtsi     |  93 +++++++++++
 3 files changed, 252 insertions(+), 1 deletion(-)

-- 
2.43.0