This cache controller is also used on the StarFive JH7110 SoC. It does
not have the data-uncorrectable ECC quirk that JH7100 has, so only
QUIRK_NONSTANDARD_CACHE_OPS is set.

Signed-off-by: Dominique Belhachemi <domibel@debian.org>
---
 drivers/cache/sifive_ccache.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/cache/sifive_ccache.c b/drivers/cache/sifive_ccache.c
index a86800b123b9..2acb8bdf06d5 100644
--- a/drivers/cache/sifive_ccache.c
+++ b/drivers/cache/sifive_ccache.c
@@ -124,6 +124,8 @@ static const struct of_device_id sifive_ccache_ids[] = {
 	{ .compatible = "sifive,fu740-c000-ccache" },
 	{ .compatible = "starfive,jh7100-ccache",
 	  .data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS | QUIRK_BROKEN_DATA_UNCORR) },
+	{ .compatible = "starfive,jh7110-ccache",
+	  .data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS) },
 	{ .compatible = "sifive,ccache0" },
 	{ /* end of table */ }
 };
-- 
2.53.0

From: Conor Dooley <conor.dooley@microchip.com>

On Thu, 30 Apr 2026 03:52:59 +0000, Dominique Belhachemi wrote:
> This cache controller is also used on the StarFive JH7110 SoC. It does
> not have the data-uncorrectable ECC quirk that JH7100 has, so only
> QUIRK_NONSTANDARD_CACHE_OPS is set.

Applied to riscv-soc-for-next, thanks!

[1/1] cache: sifive_ccache: Add StarFive JH7110 SoC support
      https://git.kernel.org/conor/c/8e2501e1494c

Thanks,
Conor.

On Thu, Apr 30, 2026 at 03:52:59AM +0000, Dominique Belhachemi wrote:
> This cache controller is also used on the StarFive JH7110 SoC. It does
> not have the data-uncorrectable ECC quirk that JH7100 has, so only
> QUIRK_NONSTANDARD_CACHE_OPS is set.

What's the motivation for enabling the nonstandard cache ops here?
The driver already binds with the generic sifive compatible on this
platform, and there's no peripherals currently supported on this
platform that need non-coherent DMA.

> 
> Signed-off-by: Dominique Belhachemi <domibel@debian.org>
> ---
>  drivers/cache/sifive_ccache.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/cache/sifive_ccache.c b/drivers/cache/sifive_ccache.c
> index a86800b123b9..2acb8bdf06d5 100644
> --- a/drivers/cache/sifive_ccache.c
> +++ b/drivers/cache/sifive_ccache.c
> @@ -124,6 +124,8 @@ static const struct of_device_id sifive_ccache_ids[] = {
>  	{ .compatible = "sifive,fu740-c000-ccache" },
>  	{ .compatible = "starfive,jh7100-ccache",
>  	  .data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS | QUIRK_BROKEN_DATA_UNCORR) },
> +	{ .compatible = "starfive,jh7110-ccache",
> +	  .data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS) },
>  	{ .compatible = "sifive,ccache0" },
>  	{ /* end of table */ }
>  };
> -- 
> 2.53.0
> 

On Thu, Apr 30, 2026 at 3:14 PM Conor Dooley <conor@kernel.org> wrote:
>
> What's the motivation for enabling the nonstandard cache ops here?
> The driver already binds with the generic sifive compatible on this
> platform, and there's no peripherals currently supported on this
> platform that need non-coherent DMA.

I am using the integrated BXE-4-32 GPU on the JH7110 with Mesa and
Vulkan on a stock Debian system (running headless so far).
To get a simple working setup, I had to patch the powervr driver
module, the device tree (both are easily patchable on the SBC)
and unfortunately, the kernel with the proposed ccache change.

See e.g.
https://github.com/domibel/linux/commit/7240d995571a13d288b5cc52097c4ebb5b339f9b
https://docs.mesa3d.org/drivers/powervr.html

The generic binding alone doesn't help, sifive,ccache0 matches but doesn't pass
QUIRK_NONSTANDARD_CACHE_OPS, so riscv_noncoherent_register_cache_ops()
is never called.

starfive,jh7110-ccache is already documented in
Documentation/devicetree/bindings/cache/sifive,ccache0.yaml .