On 4/29/26 5:08 PM, Ivan Vecera wrote:
> Rework how the fractional frequency offset (FFO) is reported in
> the DPLL subsystem.
>
> The fractional-frequency-offset-ppt attribute is moved from the
> top-level pin attributes into the pin-parent-device nested attribute
> set. This makes it consistent with phase-offset (which is already
> per-parent) and clarifies that FFO PPT represents the frequency
> difference between a pin and its parent DPLL device.
>
> The two FFO contexts are distinguished in the ffo_get callback:
> dpll=NULL for the top-level RX vs TX symbol rate offset and a valid
> dpll pointer for the nested pin vs DPLL offset.
>
> Patch 1 restructures the DPLL subsystem netlink handling, updates
> the YAML spec and driver-api documentation, and adds NULL guards
> to mlx5 and zl3073x drivers.
>
> Patch 2 implements the nested FFO for zl3073x using the
> dpll_df_offset_x register with ref_ofst=1, providing 2^-48
> resolution. The old per-reference frequency measurement is removed
> as it was redundant with measured-frequency.
>
> Ivan Vecera (2):
> dpll: move fractional-frequency-offset-ppt under pin-parent-device
> dpll: zl3073x: report FFO as DPLL vs input reference offset
>
> Documentation/driver-api/dpll.rst | 16 +++++++
> Documentation/netlink/specs/dpll.yaml | 11 +++--
> drivers/dpll/dpll_netlink.c | 34 ++++++++++----
> drivers/dpll/dpll_nl.c | 1 +
> drivers/dpll/zl3073x/chan.c | 31 ++++++++++++-
> drivers/dpll/zl3073x/chan.h | 14 ++++++
> drivers/dpll/zl3073x/core.c | 45 -------------------
> drivers/dpll/zl3073x/dpll.c | 34 +++++++-------
> drivers/dpll/zl3073x/ref.h | 14 ------
> drivers/dpll/zl3073x/regs.h | 15 +++++++
> .../net/ethernet/mellanox/mlx5/core/dpll.c | 4 ++
> 11 files changed, 126 insertions(+), 93 deletions(-)
After merge of "dpll: add pin operational state" this needs to be rebased...
Will send v2.
I.