Add QSPI controller support for the QCS615 (Talos) platform and improve
interconnect bandwidth management for QSPI controllers across multiple
Qualcomm SoCs.
The series consists of:
1. Add QCS615 compatible string to device tree bindings.
2. Add qspi-memory interconnect path support to the driver for proper DMA
bandwidth allocation.
3. Add QSPI support to QCS615 platform including OPP table, pinmux, and
controller node.
4. Enable QSPI controller and SPI-NOR flash on QCS615-RIDE board.
5. Add QSPI memory interconnect paths to existing SC7180 and Kodiak
platforms.
The key improvement in this series is adding the qspi-memory interconnect
path. Previously, the QSPI driver only managed the CPU-to-QSPI
configuration path. Add support for the QSPI-to-memory path, which is
essential for proper bandwidth allocation during DMA operations when the
QSPI controller transfers data to/from system memory.
Set the memory path bandwidth equal to the transfer speed, matching the
existing pattern used for the CPU path. Enable and disable both paths
properly during runtime PM transitions to ensure efficient power
management.
Apply this change to existing platforms (SC7180/Kodiak) as well as the
newly added QCS615 platform to ensure consistent interconnect handling
across all QSPI-enabled SoCs.
Testing:
- Verified QSPI functionality on QCS615-RIDE with SPI-NOR flash
- Confirmed proper interconnect bandwidth voting during transfers
- Validated runtime PM transitions with both interconnect paths
Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
---
Changes in v5:
- Rebased on top of current mainline to apply cleanly.
- Link to v4: https://patch.msgid.link/20260429-spi-nor-v4-0-73fb1bab03ba@oss.qualcomm.com
Changes in v4:
- Made qspi-memory node handling optional to gracefully fall back to legacy
single-region behavior when the node is absent in older Device trees.
- Checked return value of clk_bulk_prepare_enable() and logged error on
failure in resume error path.
- Fixed subject line style to match subsystem conventions
- Link to v3: https://patch.msgid.link/20260420-spi-nor-v3-0-7de325a29010@oss.qualcomm.com
Changes in v3:
- Added missing interconnect-names constraint for qcom,qcs615-qspi.
- Changed interconnect tags for qspi-memory path to QCOM_ICC_TAG_ALWAYS
- Fixed suspend sequence: now disables clocks before dropping performance
state to avoid brownout risk
- Link to v2: https://patch.msgid.link/20260414-spi-nor-v2-0-bcca40de4b5f@oss.qualcomm.com
Changes in v2:
- Moved allOf section to bottom of binding schema
- Added if:then constraint requiring minimum 2 interconnects for qcs615
- Fixed runtime PM error handling with complete goto-based cleanup
- Added proper error paths in suspend/resume functions
- Changed interconnect tags from raw 0 to QCOM_ICC_TAG_ACTIVE_ONLY
- Link to v1: https://patch.msgid.link/20260324-spi-nor-v1-0-3efe59c1c119@oss.qualcomm.com
---
Viken Dadhaniya (7):
spi: dt-bindings: qcom,spi-qcom-qspi: Add qcom,qcs615-qspi compatible
spi: spi-qcom-qspi: Fix incomplete error handling in runtime PM
spi: spi-qcom-qspi: Add interconnect support for memory path
arm64: dts: qcom: talos: Add QSPI support
arm64: dts: qcom: qcs615-ride: Enable QSPI and NOR flash
arm64: dts: qcom: kodiak: Add QSPI memory interconnect path
arm64: dts: qcom: sc7180: Add QSPI memory interconnect path
.../bindings/spi/qcom,spi-qcom-qspi.yaml | 21 +++++-
arch/arm64/boot/dts/qcom/kodiak.dtsi | 9 ++-
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 12 ++++
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++-
arch/arm64/boot/dts/qcom/talos.dtsi | 80 ++++++++++++++++++++++
drivers/spi/spi-qcom-qspi.c | 80 +++++++++++++++++++---
6 files changed, 192 insertions(+), 19 deletions(-)
---
base-commit: 0787c45ea08a13b5482e701fabc741877cf681f6
change-id: 20260324-spi-nor-09c6d9e0de05
Best regards,
--
Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>