net: phy: dp83869: fix setting CLK_O_SEL field.

[PATCH v1] net: phy: dp83869: fix setting CLK_O_SEL field.

Posted by Heiko Schocher 1 month, 3 weeks ago

Table 7-121 in datasheet says we have to set register 0xc6
to value 0x10 before CLK_O_SEL can be modified. No more infos
about this field found in datasheet. With this fix, setting
of CLK_O_SEL field in IO_MUX_CFG register worked through dts
property "ti,clk-output-sel" on a DP83869HMRGZR.

Signed-off-by: Heiko Schocher <hs@nabladev.com>
---

 drivers/net/phy/dp83869.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
index 1f381d7b13ff..96a7d255f50f 100644
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -31,6 +31,7 @@
 #define DP83869_RGMIICTL	0x0032
 #define DP83869_STRAP_STS1	0x006e
 #define DP83869_RGMIIDCTL	0x0086
+#define DP83869_ANA_PLL_PROG_PI	0x00c6
 #define DP83869_RXFCFG		0x0134
 #define DP83869_RXFPMD1		0x0136
 #define DP83869_RXFPMD2		0x0137
@@ -826,12 +827,22 @@ static int dp83869_config_init(struct phy_device *phydev)
 		dp83869_config_port_mirroring(phydev);
 
 	/* Clock output selection if muxing property is set */
-	if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK)
+	if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK) {
+		/*
+		 * Table 7-121 in datasheet says we have to set register 0xc6
+		 * to value 0x10 before CLK_O_SEL can be modified.
+		 */
+		ret = phy_write_mmd(phydev, DP83869_DEVADDR,
+				    DP83869_ANA_PLL_PROG_PI, 0x10);
+		if (ret)
+			return ret;
+
 		ret = phy_modify_mmd(phydev,
 				     DP83869_DEVADDR, DP83869_IO_MUX_CFG,
 				     DP83869_IO_MUX_CFG_CLK_O_SEL_MASK,
 				     dp83869->clk_output_sel <<
 				     DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT);
+	}
 
 	if (phy_interface_is_rgmii(phydev)) {
 		ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL,
-- 
2.20.1

Re: [PATCH v1] net: phy: dp83869: fix setting CLK_O_SEL field.

Posted by Paolo Abeni 1 month, 3 weeks ago

On 4/25/26 5:13 AM, Heiko Schocher wrote:
> Table 7-121 in datasheet says we have to set register 0xc6
> to value 0x10 before CLK_O_SEL can be modified. No more infos
> about this field found in datasheet. With this fix, setting
> of CLK_O_SEL field in IO_MUX_CFG register worked through dts
> property "ti,clk-output-sel" on a DP83869HMRGZR.
> 
> Signed-off-by: Heiko Schocher <hs@nabladev.com>

Note that a required fixes tag is missing here:

Fixes: 01db923e8377 ("net: phy: dp83869: Add TI dp83869 phy")

/P

Re: [PATCH v1] net: phy: dp83869: fix setting CLK_O_SEL field.

Posted by Heiko Schocher 1 month, 3 weeks ago

Hello Paolo,

On 28.04.26 15:50, Paolo Abeni wrote:
> On 4/25/26 5:13 AM, Heiko Schocher wrote:
>> Table 7-121 in datasheet says we have to set register 0xc6
>> to value 0x10 before CLK_O_SEL can be modified. No more infos
>> about this field found in datasheet. With this fix, setting
>> of CLK_O_SEL field in IO_MUX_CFG register worked through dts
>> property "ti,clk-output-sel" on a DP83869HMRGZR.
>>
>> Signed-off-by: Heiko Schocher <hs@nabladev.com>
> 
> Note that a required fixes tag is missing here:
> 
> Fixes: 01db923e8377 ("net: phy: dp83869: Add TI dp83869 phy")

Should I resend a v2 patch with this tag added ?

Thanks!

bye,
Heiko
> 
> /P
> 

-- 
Nabla Software Engineering
HRB 40522 Augsburg
Phone: +49 821 45592596
E-Mail: office@nabladev.com
Geschäftsführer : Stefano Babic

Re: [PATCH v1] net: phy: dp83869: fix setting CLK_O_SEL field.

Posted by Simon Horman 1 month, 3 weeks ago

On Sat, Apr 25, 2026 at 05:13:39AM +0200, Heiko Schocher wrote:
> Table 7-121 in datasheet says we have to set register 0xc6
> to value 0x10 before CLK_O_SEL can be modified. No more infos
> about this field found in datasheet. With this fix, setting
> of CLK_O_SEL field in IO_MUX_CFG register worked through dts
> property "ti,clk-output-sel" on a DP83869HMRGZR.
> 
> Signed-off-by: Heiko Schocher <hs@nabladev.com>

Reviewed-by: Simon Horman <horms@kernel.org>