From: Fangyu Yu <fangyu.yu@linux.alibaba.com>

RISC-V Svpbmt adds page-based memory types (PBMT) to PTEs, allowing
mappings to be tagged as e.g. normal memory, non-cacheable memory, or
I/O.

This series wires the RISC-V IOMMU Svpbmt capability into generic_pt
and uses PBMT to encode device memory attributes for IOMMU mappings.

---
Changes in v3:
    - Include RISCVPT_NC and RISCVPT_IO in riscvpt_attr_from_entry()
      to keep iommupt KUnit tests in sync.
    - Link to v2:
      https://lore.kernel.org/linux-riscv/20260414110212.79526-1-fangyu.yu@linux.alibaba.com
---
Changes in v2:
    - Add a comment for PT_FEAT_RISCV_SVPBMT (per Kevin and Jason).
    - Clarify PBMT encoding condition, sort PBMT-related bits by
      position, and drop the redundant PBMT clear(per Kevin).
    - Link to v1:
      https://lore.kernel.org/linux-iommu/20260411022223.91029-1-fangyu.yu@linux.alibaba.com/

Fangyu Yu (2):
  iommu/riscv: Advertise Svpbmt support to generic page table
  iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits

 drivers/iommu/generic_pt/fmt/riscv.h | 11 ++++++++++-
 drivers/iommu/riscv/iommu.c          |  2 ++
 include/linux/generic_pt/common.h    |  4 ++++
 3 files changed, 16 insertions(+), 1 deletion(-)

-- 
2.50.1

On Fri, Apr 17, 2026 at 10:07:44PM +0800, fangyu.yu@linux.alibaba.com wrote:
> Fangyu Yu (2):
>   iommu/riscv: Advertise Svpbmt support to generic page table
>   iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits
> 
>  drivers/iommu/generic_pt/fmt/riscv.h | 11 ++++++++++-
>  drivers/iommu/riscv/iommu.c          |  2 ++
>  include/linux/generic_pt/common.h    |  4 ++++
>  3 files changed, 16 insertions(+), 1 deletion(-)

Applied this one instead of v2.

>> Fangyu Yu (2):
>>   iommu/riscv: Advertise Svpbmt support to generic page table
>>   iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits
>>
>>  drivers/iommu/generic_pt/fmt/riscv.h | 11 ++++++++++-
>>  drivers/iommu/riscv/iommu.c          |  2 ++
>>  include/linux/generic_pt/common.h    |  4 ++++
>>  3 files changed, 16 insertions(+), 1 deletion(-)
>
>Applied this one instead of v2.

Thanks for the review and for applying this version. I’ve sent a v4
update to fix the 32-bit build warning, so please use the v4 series
going forward.

v4: https://lore.kernel.org/linux-riscv/20260512074142.16356-1-fangyu.yu@linux.alibaba.com

Reported-by: kernel test robot <lkp@intel.com> in [1].
[1] https://lore.kernel.org/oe-kbuild-all/202605121350.wZxB51k0-lkp@intel.com/

Thanks,
Fangyu

On Tue, May 12, 2026 at 03:53:39PM +0800, fangyu.yu@linux.alibaba.com wrote:
> >> Fangyu Yu (2):
> >>   iommu/riscv: Advertise Svpbmt support to generic page table
> >>   iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits
> >>
> >>  drivers/iommu/generic_pt/fmt/riscv.h | 11 ++++++++++-
> >>  drivers/iommu/riscv/iommu.c          |  2 ++
> >>  include/linux/generic_pt/common.h    |  4 ++++
> >>  3 files changed, 16 insertions(+), 1 deletion(-)
> >
> >Applied this one instead of v2.
> 
> Thanks for the review and for applying this version. I’ve sent a v4
> update to fix the 32-bit build warning, so please use the v4 series
> going forward.

Since Joerg already applied it the normal thing is to send a fixup
patch to correct the bot warning

Jason