From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi all,

This patch series addresses several issues with the PM register caching
implementation in the Renesas RZ/G2L pinctrl driver. The changes include:
- Fixing SMT register caching to account for the split SMT registers on
  RZ/V2H(P).
- Adding caching for the SR (Slew Rate) registers during PM suspend/resume.
- Handling the IOLH configuration for RZ/V2H(P) in the PM cache setup.
- Adding caching for the NOD (N-ch Open Drain) registers during PM
  suspend/resume.
- Ensuring that PUPD registers for dedicated pins on RZ/V2H(P) are included
  in the PM cache.

v1->v2:
- Patches 1, 3, 4, and 5 are new.
- Patch 2 has been updated to include a dedicated cache for SR registers
  as pointed by sashiko.dev.

Cheers,
Prabhakar

Lad Prabhakar (5):
  pinctrl: renesas: rzg2l: Fix SMT register cache handling
  pinctrl: renesas: rzg2l: Add SR register cache for PM suspend/resume
  pinctrl: renesas: rzg2l: Handle RZ/V2H(P) IOLH configuration in PM
    cache
  pinctrl: renesas: rzg2l: Add NOD register cache for PM suspend/resume
  pinctrl: renesas: rzg2l: Handle PUPD for RZ/V2H(P) dedicated pins in
    PM

 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 113 +++++++++++++++++++++---
 1 file changed, 102 insertions(+), 11 deletions(-)

-- 
2.53.0